Timothy A Pontius

US Patent:

6337893, Jan 8, 2002

Filed:

Aug 23, 2000

Appl. No.:

09/644348

Inventors:

Timothy A. Pontius - Lake in the Hills IL

Assignee:

Philips Electronics North America Corp. - New York NY

International Classification:

H03K 2364

US Classification:

377108, 377 26, 377 34

Abstract:

A gray-code counter system (AP1) for a RAM-based FIFO comprises a read pointer ( ), a write pointer ( ), and a detector ( ). The read pointer includes a gray-code decoder ( ), a binary incrementer ( ), a gray-code encoder ( ), and a register ( ) that holds the pointer count). The binary incrementer increments by 1 except when the input is 0110 (decimal ) or 1110 (decimal ); in these cases, it increments by 3. The result is a 4-bit modulo- gray-code sequence with the twelve allowed gray-code values being distributed among the sixteen possible 4-bit gray code values with translational and reflective bilateral symmetry. The write pointer is similar. Because of the translational symmetry, detectors that work with counters with modulo numbers that are power of two work with the corresponding non-power-of-two counter to provide âfullâ and âemptyâ indications. When read and write counts differ at the two most-significant bit positions but are equal at the remaining bit positions, the detector provides a âfullâ indication for a 6-count FIFO. The gray-code counter design is scaleable to any non-power-of-two modulo number divisible by four.

US Patent:

6467010, Oct 15, 2002

Filed:

Feb 25, 2000

Appl. No.:

09/513009

Inventors:

Timothy Pontius - Lake In The Hills IL
Mark Johnson - Elgin IL

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G06F 1340

US Classification:

710305, 710314

Abstract:

A method and arrangement passes data between two busses without needing conventional bridge-interface protocols. Consistent with one method embodiment of the present invention, data is passed between a first bus on a reference chip and an external bus using a two-way buffer arrangement between the external bus and the first bus. The method includes coupling a two-way buffer arrangement between the external bus and the first bus, determining which of the busses is the initiating bus, and in response to this determination, controlling the two-way buffer arrangement to asynchronously copy data through the two-way buffer arrangement from the initiating bus to the other bus, wherein data is passed automatically in response to its presence at the buffer arrangement without any clock cycle delays. An example application is directed to interfacing with a bus used for a rapid silicon processing chip.

US Patent:

6507887, Jan 14, 2003

Filed:

Apr 18, 2000

Appl. No.:

09/551087

Inventors:

Timothy A. Pontius - Lake in the Hills IL
Gregory E. Ehmann - Sleepy Hollow IL

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G06F 1200

US Classification:

711102, 711104, 711170

Abstract:

A method of designing a mask-programmable random-access read-only memory device begins with a step of assigning weightings to addresses according to their expected frequency of access. These weighting are used in a second step of determining for each sense amplifier, what is the low-power sense (inverted or uninverted) of the stored bits using that sense amplifier as an output. The third step involves storing the data in the low-power sense. The fourth step involves inverting the outputs for the data that is stored inverted. This can involve using sense inverting sense amplifiers for inverted data and sense preserving amplifiers for uninverted data. The method can result in memories in which some outputs are sense inverting while others are sense preserving. The result is a memory device with reduced power consumption relative to a comparable design not taking advantage of the relationship between data values and power consumption.

US Patent:

6513105, Jan 28, 2003

Filed:

May 7, 1999

Appl. No.:

09/307164

Inventors:

Timothy A. Pontius - Lake in the Hills IL

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G06F 1200

US Classification:

711209, 710 33, 710 65, 710305, 710310

Abstract:

A computer system includes a RAM-based FIFO for buffering communications between a host processor and a remote serial-communications device. The FIFO provides for quadlet, doublet, and singlet transfer widths depending on the memory-mapped IO address asserted by the processor. Quadlet transfers can be implemented until the amount of data remaining to be transferred is less than four bytes. For each quadlet transfer, the read pointer, in the case of a read operation, or the write pointer, in the case of a write operation, is incremented by four. If two or three bytes of data remain after the quadlet transfers, a doublet transfer can be implemented; in this case, the appropriate pointer is incremented by two. Finally, if a byte of data remains after the quadlet transfers and a possible doublet transfer, then a singlet transfer is effected. In this case, the appropriate pointer is incremented by one.

US Patent:

6542855, Apr 1, 2003

Filed:

May 10, 1999

Appl. No.:

09/309137

Inventors:

Timothy A. Pontius - Lake in the Hills IL

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G06F 1500

US Classification:

702186, 712241, 714 6, 717 9

Abstract:

A method of selecting a cache design for a computer system begins with the making of a prototype module with a processor, a âseedâ cache, and a trace detection module. The prototype module can be inserted within a system that includes main memory and peripherals. While an application program is run on the system, the communications between the processor and the seed cache are detected and compressed. The compressed detections are stored in a trace capture module and collectively define a trace of the program on the prototype module. The trace is then expanded and used to evaluate a candidate cache design. The expansion and evaluation can be iterated to evaluate many cache designs. The method can be used to pick the cache design with the best performance or as a foundation for performing a cost/performance comparison of the evaluated caches. In this method, a single prototype is used to generate an accurate trace that permits many alternative cache designs to be evaluated.

US Patent:

6543030, Apr 1, 2003

Filed:

May 7, 1999

Appl. No.:

09/307165

Inventors:

Liewei Bao - Hoffman Estates IL
Timothy A. Pontius - Lake in the Hills IL

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G06F 1750

US Classification:

716 2, 716 3, 716 18, 326 41

Abstract:

The timing characteristics of an integrated circuit design with an original combination-logic module can be potentially improved by moving an input signal with problematic timing in the original module so that it controls an output multiplexer in a revised module. The revised module includes two submodules. The first submodule provides the desired logic result where the late signal is low; the second submodule provides the desired logic result where the late signal is high. The multiplexer is controlled by the late signal so that its output is the desired logic result under steady-state conditions. If there are other input signals requiring timing advancement, the method can be reiterated. The method can be iterated until specifications are met or it is clear that the method cannot meet specifications by additional iterations.

US Patent:

6636166, Oct 21, 2003

Filed:

May 31, 2001

Appl. No.:

09/871197

Inventors:

D. C. Sessions - Phoenix AZ
Ivan Svestka - North Riverside IL
David R. Evoy - Tempe AZ
Timothy Pontius - Lake in the Hills IL
Mark Johnson - Elgin IL
Arjan Bink - Chicago IL

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

H03M 700

US Classification:

341 63

Abstract:

In one example embodiment, data is transferred at high speeds over a parallel data bus without loss of data integrity by transferring the data encoded with the quantity of ones relatively the same as the quantity of zeroes. Consistent with one embodiment of the present invention, a bus-interface circuit encodes a set of X data bits into a set of Y data bits, where Y is greater than X. The encoding is implemented to approximately balance the number of ones and the number of zeroes in each set to be transmitted. A specific example application involves encoding the set of X data bits so that there is a balanced number of ones and zeroes in the set of Y data bits. In certain applications, the present invention is implemented to reduce current flow between transmitting and receiving modules and thereby reduce EMI, reduce the number of power pins required for the bus interface, and/or reduce the I/O delay and the skew from voltage sag in the signals passed over the parallel data bus.

US Patent:

6839862, Jan 4, 2005

Filed:

May 31, 2001

Appl. No.:

09/871159

Inventors:

David R. Evoy - Tempe AZ, US
Timothy Pontius - Lake in the Hills IL, US
Gregory E. Ehmann - Sleepy Hollow IL, US

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G06F 104
G06F 112
G04L 700

US Classification:

713503, 713400, 713600

Abstract:

In one example embodiment, a high-speed parallel-data communication approach transfers digital data in parallel from a first module to a second module over a communication channel including a plurality of parallel data-carrying lines and a clock path. The parallel bus lines are arranged in a plurality of groups, each of the groups including a plurality of data-carrying lines and a clock path adapted to carry a clock signal for synchronizing digital data carried from the first module to the second module. The sets of data are concurrently transferred using the groups of lines of the parallel bus, and at the second module and for each group, the transferred digital data is synchronously collected via the clock signal for the group. At the second module, the data collected for each group is aligned. By grouping the bus lines in groups with each group having its own clock domain, skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.