Prithviraj R Banerjee

US Patent:

7086040, Aug 1, 2006

Filed:

Jan 30, 2001

Appl. No.:

09/773211

Inventors:

Pramod G. Joisha - Evanston IL, US
Prithviraj Banerjee - Glenview IL, US
Nagaraj Shenoy - Karnataka, IN

Assignee:

Northwestern University - Evanston IL

International Classification:

G06F 9/45

US Classification:

717137, 717141, 717136, 717140

Abstract:

A method for inferring the shape and dimension of arrays for high-level, array-based languages such as MATLAB is presented. The method uses the algebraic properties that underlie MATLAB's shape semantics and infers the shape that the program expression assumes. In one embodiment, a shape-tuple of the result of a program expression is inferred by creating a shape-tuple expression comprising the shape-tuples of the operands and the shape-tuple operator.

US Patent:

7376939, May 20, 2008

Filed:

Feb 7, 2002

Appl. No.:

10/072212

Inventors:

Anshuman Nayak - Schaumburg IL, US
Malay Haldar - Schaumburg IL, US
Alok Choudhary - Chicago IL, US
Vikram Saxena - Schaumburg IL, US
Prithviraj Banerjee - Glenview IL, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 9/45
G06F 9/455
G06F 17/50
G06F 7/62
G06F 9/44

US Classification:

717144, 717136, 717138, 717139, 717140, 717114, 717146, 713 13, 713 23, 716 1

Abstract:

Electronic design automation tool specifies an architecture at a system level and its component (which include intellectual property (IP) cores like embedded processors, arithmetic logic units (ALU), multipliers, dividers, embedded memory element, programmable logic cells, etc. ); specifies IP-cores and their interface; and understands IP-cores and functions via their interface. Further, techniques are provided for modeling the timing behavior of a function or functional block without drawing a timing diagram; understanding the interface behavior of a function block which captures the timing waveforms; specifying virtual functions which are built using basic functional units and their timing behavior; parsing and creating an internal graphical form for analyzing a specification for compilation; matching the components in the architecture specification and their instantiation to map the computations in the input graph produced from an application; and mapping the specification onto the target's components.

US Patent:

20020048360, Apr 25, 2002

Filed:

Apr 6, 2001

Appl. No.:

09/827499

Inventors:

Rajan Zambre - Westford MA, US
Mahesh Danke - Chelmsford MA, US
Prithviraj Banerjee - North Chelmsford MA, US

International Classification:

H04M007/00

US Classification:

379/229000, 379/221080

Abstract:

The functions of a Signaling System 7 (SS7) network node are divided among multiple nodes of an Internet Protocol (IP) network. An “A” node includes an SS7 application component, and a “P” node includes an SS7 transport component connected to the SS7 network. Each node also includes an IP transport component and an adapter for translating messages between IP and SS7 protocols. The A nodes and P nodes inter-operate via the IP network in a manner invisible to the SS7 network and the SS7 application component. Each adapter requests a connection to a counterpart adapter from a connectivity manager for each transaction. The connectivity manager, which may be centralized or distributed in the IP network, allocates adapters to transactions and informs requesting adapters of the allocations. For load sharing, the connectivity manager weights the adapters by their transaction processing capacities and allocates adapters in proportion to their respective weights.

US Patent:

20040019883, Jan 29, 2004

Filed:

Jan 26, 2001

Appl. No.:

09/770541

Inventors:

Prithviraj Banerjee - Glenview IL, US
Alok Choudhary - Chicago IL, US
Malay Haldar - Evanston IL, US
Anshuman Nayak - Evanston IL, US

Assignee:

NORTHWESTERN UNIVERSITY

International Classification:

G06F009/45

US Classification:

717/152000, 717/150000, 717/159000

Abstract:

Digital circuit is synthesized from algorithm described in the MATLAB programming language. A MATLAB program is compiled into RTL-VHDL, which is synthesizable using system-specific tools to develop ASIC or FPGA configuration. Intermediate transformations and optimizations are performed to obtain highly optimized description in RTL-VHDL or RTL Verilog of given MATLAB program. Optimizations include levelization, scalarization, pipelining, type-shape analysis, memory optimizations, precision analysis and scheduling.

Author:

Prithviraj Banerjee

ISBN #:

0130158356

Author:

Prithviraj Banerjee

ISBN #:

3540669078