Nicholas K Kucharewski

US Patent:

20130329558, Dec 12, 2013

Filed:

Jun 7, 2012

Appl. No.:

13/490896

Inventors:

Nicholas Kucharewski - San Jose CA, US
Martin Lund - Los Altos Hills CA, US

Assignee:

BROADCOM CORPORATION - Irvine CA

International Classification:

H04L 12/24

US Classification:

370235

Abstract:

A system provides burst absorption of network traffic. The system may include multiple physical (PHY) layer devices in communication with a switch device. The switch device may instruct a PHY layer device to send incoming data received by the PHY layer device at a throttled rate, for example when the switch device identifies a high level of network congestion in the switch. The PHY layer device may absorb the burst of incoming network traffic by buffering incoming data in a queue and sending the incoming data to the queue at a throttled data transfer rate. When the network congestion has been alleviated, the PHY layer device may transmit network traffic to the switch at an accelerated transfer rate to empty the network traffic buffered in the queue.

US Patent:

53571533, Oct 18, 1994

Filed:

Jan 28, 1993

Appl. No.:

8/010378

Inventors:

David Chiang - Saratoga CA
Napoleon W. Lee - Fremont CA
Thomas Y. Ho - Milpitas CA
David A. Harrison - Cupertino CA
Nicholas Kucharewski - Pleasanton CA
Jeffrey H. Seltzer - San Jose CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19177

US Classification:

307465

Abstract:

A programmable logic device having macrocells enables gate cascades between macrocells to occur with a faster signal transit time, while preserving the flip flop function of the cascaded macrocells by reallocating a redirectable flip flop reset product term to the flip flop input. All gate product terms are retained during cascading. The macrocell logic is optimized for fast signal transit with selectable flip flop clocking. Multiplex clocking and programming are done with fewer transistors in the signal path, further reducing signal transit time.

US Patent:

55303781, Jun 25, 1996

Filed:

Apr 26, 1995

Appl. No.:

8/430207

Inventors:

Nicholas Kucharewski - Pleasanton CA
David Chiang - Saratoga CA
Jesse H. Jenkins - Danville CA

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41

Abstract:

An erasable programmable logic device (EPLD) includes function blocks connected by a universal interconnect matrix (UIM). The UIM includes both a cross-point circuit and a multiplexer-based (MUX-based) circuit. The cross-point circuit includes intersecting first and second conductors programmably connected by memory cells having control gates connected to the first conductors, drains connected to the second conductors, and sources connected to ground. The MUX-based circuit includes third and fourth conductors programmably connected by pass-gates having first terminals connected to the third conductors, second terminals connected to the fourth conductors, and gates connected to memory cells. The UIM further includes multiple-input multiplexers having first input lines connected to the cross-point circuit, second input lines connected to the MUX-based circuit, and output lines connected to the input lines of the function blocks. The multiple-input multiplexers are programmable to selectively apply signals from either the cross-point circuit or the MUX-based circuit to the function block input lines.

US Patent:

55065236, Apr 9, 1996

Filed:

Mar 1, 1994

Appl. No.:

8/204717

Inventors:

David Chiang - Saratoga CA
Nicholas Kucharewski - Pleasanton CA

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

G11C 700

US Classification:

327 57

Abstract:

The present invention provides a sense circuit including a first bit line, a second bit line, a first plurality of memory cells coupled to the first bit line, a second plurality of memory cells coupled to the second bit line, and selection circuitry coupled to the first bit line and the second bit line. The selection circuitry provides a wide AND gate function in one mode and provides a zero power circuit for generating a function of a single input in another mode.

US Patent:

55700519, Oct 29, 1996

Filed:

May 31, 1995

Appl. No.:

8/454908

Inventors:

David Chiang - Saratoga CA
Napoleon W. Lee - Fremont CA
Thomas Y. Ho - Milpitas CA
Nicholas Kucharewski - Pleasanton CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 3289

US Classification:

327203

Abstract:

A memory device, with increased storage speed and enhanced memory utilization, can be implemented by using multiplex clocking and efficient device design and enhanced flip-flop utilization. Transit time through the circuit, and hence circuit speed, can be controlled through multiplexed clock signals, and is increased by using fewer transistors in the signal path and allowing data to be transmitted directly to the flip-flop output by bypassing the flip-flop's master latch input.

US Patent:

57421781, Apr 21, 1998

Filed:

Oct 22, 1996

Appl. No.:

8/740118

Inventors:

Jesse H. Jenkins - Danville CA
Nicholas Kucharewski - Pleasanton CA
David Chiang - Saratoga CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19003

US Classification:

326 33

Abstract:

In a programmable logic device having a plurality of external pins each of which may be driven by an output drive structure controlled by a programmable logic block, a logic device such as an OR gate or a programmable pull-up or pull-down switch is inserted between the input terminal of the output drive structure and the programmable logic block or other internal logic block which controls the output driver. This inserted structure allows the macrocell to be used for internal logic while the output drive structure is used to stabilize power or ground voltage.

US Patent:

55657923, Oct 15, 1996

Filed:

Sep 6, 1994

Appl. No.:

8/301504

Inventors:

David Chiang - Saratoga CA
Napoleon W. Lee - Fremont CA
Thomas Y. Ho - Milpitas CA
David A. Harrison - Cupertino CA
Nicholas Kucharewski - Pleasanton CA
Jeffrey H. Seltzer - San Jose CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19177

US Classification:

326 40

Abstract:

A programmable logic device having macrocells enables gate cascades between macrocells to occur with a faster signal transit time, while preserving the flip flop function of the cascaded macrocells by reallocating a redirectable flip flop reset product term to the flip flop input. All gate product terms are retained during cascading. The macrocell logic is optimized for fast signal transit with selectable flip flop clocking. Multiplex clocking and programming are done with fewer transistors in the signal path, further reducing signal transit time.

US Patent:

57640769, Jun 9, 1998

Filed:

Jun 26, 1996

Appl. No.:

8/670472

Inventors:

Napoleon W. Lee - Milpitas CA
Derek R. Curd - San Jose CA
Jeffrey H. Seltzer - Los Gatos CA
Jeffrey Goldberg - San Jose CA
David Chiang - Saratoga CA
Kameswara K. Rao - San Jose CA
Nicholas Kucharewski - Pleasanton CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19177

US Classification:

326 38

Abstract:

A complex programmable logic device (PLD) that includes a number of programmable function blocks and an instruction bus for receiving programming instructions. The programming instructions are used to program the function blocks to enable the PLD to perform one or more desired logic functions. The PLD also includes an instruction-blocking circuit that is connected to each of the functional blocks. When directed by a user, the instruction blocking circuit selectively blocks programming instructions on the instruction bus from one or more of the function blocks while allowing the other function blocks to receive the programming instructions. Thus, one or more function blocks in the PLD are reprogrammed without interrupting the operation of the remaining function blocks.