Ansys, Inc.
Senior Application Engineer - Rtl Low Power Design Methodology
Synopsys Aug 2013 - Jul 2017
Senior Corporate Application Engineer - Test Automation Products
Nvidia Feb 2013 - May 2013
Dft-Mbist Design Intern
Fairchild Semiconductor Oct 2012 - Dec 2012
Test Engineering Intern
On Semiconductor Jun 2012 - Aug 2012
Product and Test Engineering Intern
Education:
San Jose State University 2011 - 2013
Master of Science, Masters, Electrical Engineering
Dwarkadas J. Sanghvi College of Engineering 2008 - 2011
Bachelor of Engineering, Bachelors, Engineering, Electronics Engineering
Skills:
Vlsi Cad Test Processes Pre Sales Post Sales Support Methodology Implementation Logic Synthesis Specifications Review Product Evaluations Dft Scan Troubleshooting Testing Unix Shell Scripting Debugging Tcl Perl Python Digital Logic Design Integrated Circuit Design Static Timing Analysis Unix Rtl Design Hardware Design Asic Semiconductors Vlsi Soc Verilog Gnu Make System on A Chip Very Large Scale Integration
DFT Santa Clara, CA Mar 2013 to May 2013 Hardware InternFairchild Semiconductor San Jose, CA Sep 2012 to Nov 2012 Post Silicon Validation InternIP Cores
Sep 2012 to Nov 2012Bit First
Sep 2012 to Nov 2012ON Semiconductor Santa Clara, CA Jun 2012 to Aug 2012 Product Engineering InternKeypad Scanner and Encoder
Sep 2011 to Nov 2011
Education:
San Jose State University San Jose, CA Aug 2011 to May 2013 Master of Science in Electrical EngineeringMumbai University- D.J. Sanghvi College of Engineering Mumbai, Maharashtra Aug 2008 to Jul 2011 Bachelor of Engineering in Electronics EngineeringVivekananda Education Society Polytechnic Mumbai, Maharashtra Aug 2005 to May 2008 Diploma in Industrial Electronic