Kyung Oak Oh

Address:

1836 Chantilly Ln, Fullerton, CA 92833

VIN:

JTHBL46F885077909

Make:

LEXUS

Model:

LS 460

Year:

2008

US Patent:

20090235688, Sep 24, 2009

Filed:

Aug 1, 2008

Appl. No.:

12/221291

Inventors:

Kyung Ja Oh - Los Angeles CA, US

International Classification:

A44C 7/00

US Classification:

63 141, 63 12, 63 145, 606204

Abstract:

This invention is about wearing earring that stimulates the acupoints of the ear and provides easy wearing with beautiful feature. In detail, it is consisted of a pair of parts formed to press a specific part of the ear; a connecting part that links above-mentioned parts together; a decoration for the surfaces of a pair of above-mentioned parts or connecting part; a stimulating protrusion part combined with at least a part of above-mentioned pairs to stimulate acupoints.

US Patent:

20110119425, May 19, 2011

Filed:

Jun 30, 2008

Appl. No.:

12/675105

Inventors:

Ravindranath Kollipara - Palo Alto CA, US
Xingchao Yuan - Palo Alto CA, US
Frank Lambrecht - mountain View CA, US
Ming Li - Fremont CA, US
Richard E. Perego - Thornton CO, US
Qi Lin - Mountain View CA, US
David Nguyen - Cupertino CA, US
Kyung Suk Oh - Campbell CA, US

Assignee:

RAMBUS INC. - Los Altos CA

International Classification:

G06F 13/40
G06F 13/20

US Classification:

710307, 710313

Abstract:

The disclosure relates to a detachable signalling interconnect apparatus that provides connectivity between two or more components of a memory system in conjunction with different modes of operation of the components. The memory system comprises: a first socket to receive a first memory module; a second socket to receive a second memory module; a detachable signal-interconnect; and a memory controller coupled to the detachable signal-interconnect and configured to define a first mode of operation and a second mode of operation, wherein in the first mode of operation the detachable signal-interconnect is to couple the memory-controller to the first memory module and in the second mode of operation the detachable signal-interconnect is to couple the memory controller to the first memory module and the second memory module.

US Patent:

20200195475, Jun 18, 2020

Filed:

Dec 13, 2019

Appl. No.:

16/714178

Inventors:

- Sunnyvale CA, US
Brian Leibowitz - San Francisco CA, US
Hae-Chang Lee - Los Altos CA, US
Jihong Ren - Sunnyvale CA, US
Kyung Suk Oh - Cupertino CA, US
Jared L. Zerbe - Woodside CA, US

International Classification:

H04L 25/03
H04L 12/26
H04L 7/00
H04L 7/033

Abstract:

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

US Patent:

20170338979, Nov 23, 2017

Filed:

Aug 7, 2017

Appl. No.:

15/670916

Inventors:

- Sunnyvale CA, US
Brian Leibowitz - San Francisco CA, US
Hae-Chang Lee - Los Altos CA, US
Jihong Ren - Sunnyvale CA, US
Kyung Suk Oh - Cupertino CA, US
Jared L. Zerbe - Woodside CA, US

International Classification:

H04L 25/03
H04L 7/00
H04L 12/26
H04L 7/033

Abstract:

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

US Patent:

20170054576, Feb 23, 2017

Filed:

Sep 8, 2016

Appl. No.:

15/259662

Inventors:

- Sunnyvale CA, US
Brian Leibowitz - San Francisco CA, US
Hae-Chang Lee - Los Altos CA, US
Jihong Ren - Sunnyvale CA, US
Kyung Suk Oh - Cupertino CA, US
Jared L. Zerbe - Woodside CA, US

International Classification:

H04L 25/03
H04L 12/26
H04L 7/00

Abstract:

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

US Patent:

20160142200, May 19, 2016

Filed:

Sep 29, 2015

Appl. No.:

14/868721

Inventors:

- Sunnyvale CA, US
Brian Leibowitz - San Francisco CA, US
Hae-Chang Lee - Los Altos CA, US
Jihong Ren - Sunnyvale CA, US
Kyung Suk Oh - Cupertino CA, US
Jared L. Zerbe - Woodside CA, US

International Classification:

H04L 7/033
H04L 25/03
H04L 7/00

Abstract:

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

US Patent:

20140169438, Jun 19, 2014

Filed:

Aug 29, 2013

Appl. No.:

14/014047

Inventors:

- Sunnyvale CA, US
Brian Leibowitz - San Francisco CA, US
Hae-Chang Lee - Los Altos CA, US
Jihong Ren - Sunnyvale CA, US
Kyung Suk Oh - Cupertino CA, US
Jared L. Zerbe - Woodside CA, US

Assignee:

Rambus Inc. - Sunnyvale CA

International Classification:

H04L 7/033
H04L 25/03

US Classification:

375232

Abstract:

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.