Kevin M Mcilvain from Austin, TX, age 47

Us Patents

Negative Slack Recoverability Factor—A Net Weight To Enhance Timing Closure Behavior
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US Patent:

7305644, Dec 4, 2007
Filed:

May 16, 2005
Appl. No.:

11/129785
Inventors:

James J. Curtin - Fishkill NY, US
Kevin M. McIlvain - Cold Spring NY, US
Ray Raphy - Poughkeepsie NY, US
Douglas S. Search - Red Hook NY, US
Stephen Szulewski - Newburgh NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 17/50
G06F 9/45
US Classification:

716 10, 716 6
Abstract:

More “timing closure efficient” Timing Driven Placements by implementing our new net weight for negative slack paths to enhance timing closure behavior is provided by a NSRF (Negative Slack Recover Factor). This new weight would not be based on the absolute amount of negative slack in a path, but rather it would be based on the proportion or percentage of the path's total net delay adder that must be recovered in order to achieve timing closure (zero slack). After an initial or previous placement has been created, then a list of paths with timing violations with a Negative Slack Recover Factor (NSRF) is created for each net in each of the timing paths on the list of paths, and then calculating a NSRF net weight factor for use in subsequent placements and also assigning nets in the list of paths with no timing violations a NSRF default value of one. The NSRF value is calculated as equaling (ZWLM slack value+negative slack value)/ZWLM slack value=(1+(negative slack value/ZWLM slack value)), where ZWLM is a Zero Wire Load Model (ZWLM) value of timing wherein all wire parasitics are removed from consideration in the timing.

Genie: A Method For Classification And Graphical Display Of Negative Slack Timing Test Failures
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US Patent:

7356793, Apr 8, 2008
Filed:

May 16, 2005
Appl. No.:

11/129784
Inventors:

James J. Curtin - Fishkill NY, US
Edward J. Hughes - Archbald PA, US
Kevin M. McIlvain - Cold Spring NY, US
Jose L. Neves - Poughkeepsie NY, US
Ray Raphy - Poughkeepsie NY, US
Douglas S. Search - Red Hook NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 17/50
US Classification:

716 6, 716 11, 703 16
Abstract:

Genie is a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.

Method For Netlist Path Characteristics Extraction
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US Patent:

20060010411, Jan 12, 2006
Filed:

May 16, 2005
Appl. No.:

11/129786
Inventors:

James Curtin - Fishkill NY, US
Kevin McIlvain - Cold Spring NY, US
Ray Raphy - Poughkeepsie NY, US
Douglas Search - Red Hook NY, US
Stephen Szulewski - Newburgh NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

G06F 17/50
US Classification:

716006000
Abstract:

A circuit design method utilizes existing late mode worst case slack calculation functions inherent in timing path trace algorithms which only need to record the worst arrival and worst required arrival times at each netlist node as traced paths. Because of this, most individual path tracing is curtailed due to the likelihood that a more critical arrival or required arrival time has already been recorded at a given netlist node. Worst case slacks are then determined by subtracting the worst case arrival time from the worst case required arrival time. In this manner, worst case slack values are calculated for the entire netlist within a reasonable amount of time. The method uses these existing functions by querying the worst case slack at each netlist node under varied timing model scenarios. These varied timing model scenarios include altering the cell and net delays and arrival times in the model. Then, with the worst case slacks from the varied timing model scenarios in hand, the required priority factors, recoverability and path composition factors are computed by comparing the differences in the worst case slack at each netlist node.

Chip Having Timing Analysis Of Paths Performed Within The Chip During The Design Process
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US Patent:

20080066036, Mar 13, 2008
Filed:

Nov 5, 2007
Appl. No.:

11/934995
Inventors:

James Curtin - Fishkill NY, US
Michael Cadigan - Brewster NY, US
Edward Hughes - Archbald PA, US
Kevin McIlvain - Cold Spring NY, US
Jose Neves - Poughkeepsie NY, US
Ray Raphy - Poughkeepsie NY, US
Douglas Search - Red Hook NY, US
Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:

G06F 17/50
US Classification:

716006000
Abstract:

An integrated Circlet chip is made using Genie, a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.

Packeted Protocol Device Test System
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US Patent:

20210286694, Sep 16, 2021
Filed:

Mar 16, 2020
Appl. No.:

16/819512
Inventors:

- Armonk NY, US
Kevin M. Mcilvain - Delmar NY, US
Gary A. Van Huben - Poughkeepsie NY, US
International Classification:

G06F 11/27
G06F 13/40
G06F 13/28
Abstract:

Aspects include configuring a plurality of functional self-test controllers in a test control device to run a plurality of functional test cases in parallel on a plurality of devices under test. Test traffic is arbitrated between the functional self-test controllers and a plurality of packeted protocol layer interfaces of the test control device. One or more protocol specific conversions are performed between the test traffic and a device-specific packeted protocol of each of the devices under test. Payload checking is performed between the packeted protocol layer interfaces and the devices under test to verify responses of the devices under test to the functional test cases.

Using Spare Bits In Memory Systems
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US Patent:

20210141550, May 13, 2021
Filed:

Nov 8, 2019
Appl. No.:

16/677740
Inventors:

- Armonk NY, US
David D. Cadigan - Danbury CT, US
Kevin M. McIlvain - Delmar NY, US
International Classification:

G06F 3/06
G11C 14/00
Abstract:

Disclosed is a computer implemented method to mark data as persistent using spare bits. The method includes receiving, by a memory system, a set of data, wherein the set of data includes a subset of meta-bits, and the set of data is received as a plurality of transfers, and wherein the memory system includes a first rank and a second rank. The method also includes decoding, by a decoder, the subset of meta-bits, wherein the subset of meta-bits are configured to indicate the set of data is important. The method further includes storing, based on the decoding, the set of data in a persistent storage medium.

Efficient And Selective Sparing Of Bits In Memory Systems
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US Patent:

20200226040, Jul 16, 2020
Filed:

Mar 24, 2020
Appl. No.:

16/828380
Inventors:

- Armonk NY, US
Warren E. Maule - Cedar Park TX, US
Kevin M. Mcilvain - Delmar NY, US
International Classification:

G06F 11/16
G11C 29/42
G11C 29/00
G06F 11/10
G11C 29/44
G11C 29/52
Abstract:

A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

Using Dual Channel Memory As Single Channel Memory With Spares
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US Patent:

20200075079, Mar 5, 2020
Filed:

Nov 5, 2019
Appl. No.:

16/674235
Inventors:

- Armonk NY, US
Warren E. Maule - Cedar Park TX, US
Kevin M. Mcilvain - Delmar NY, US
Saravanan Sethuraman - Bangalore, IN
International Classification:

G11C 11/4076
G11C 11/24
G11C 11/4093
G11C 29/00
G11C 16/04
G11C 29/04
G11C 5/04
Abstract:

A technique relates to operating a memory controller. The memory controller drives first memory devices and second memory devices of the memory controller in a dual channel mode. A first error correcting code (ECC) memory device and a second ECC memory device protect the first memory devices and the second memory devices. The memory controller drives the first memory devices and the second memory devices in a single channel mode such that the second ECC memory device is a spare memory device, and the first ECC memory device protects the first memory devices and the second memory devices. The memory controller is configured to switch between the dual channel mode and the single channel mode.