Kent Y Okasaki

US Patent:

59235683, Jul 13, 1999

Filed:

Mar 31, 1997

Appl. No.:

8/831443

Inventors:

Soo-Young Oh - Fremont CA
Kent Okasaki - Santa Clara CA
John L. Moll - Los Altos CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1750

US Classification:

364490

Abstract:

A method of estimating the distributed capacitance of an interconnection line within an integrated circuit. The invention includes a method for estimating distributed capacitance between interconnection lines within an integrated circuit. The integrated circuit is modeled as including a middle plane which is planar and adjacent to a top plane and a bottom plane. Each plane includes a plurality of interconnection lines which are infinite in length and parallel. The interconnection lines of the middle plane are orthogonal to the interconnection lines of the top plane and the interconnection lines of the bottom plane. A ground plane is adjacent and planar to the bottom plane. A first value of capacitance between an interconnection line of the middle plane and an interconnection line of the top plane is estimated ignoring the effects of the bottom plane. A second value of capacitance between the interconnection line of the middle plane and the interconnection line of the top plane is estimated assuming the bottom plane is a solid conductive sheet. An actual value of capacitance between the interconnection line of the middle plane and the interconnection line of the top plane is estimated by interpolating between the first value of capacitance and the second value of capacitance.