A photo-sensing device package and the method of packaging such device is provided. The package includes an assembly portion having a substrate formed of a material substantially transparent to light within a predetermined range of wavelengths; a sensing portion including at least one photo-sensing die photo-electronically transducing light within the predetermined range of wavelengths; and, a plurality of first solder joints joining the sensing and assembly portions. The assembly portion is formed with at least a first metal layer disposed on the substrate about a front surface region thereof; and, at least one passivation layer formed to extend over the first metal layer. The passivation layer is patterned to define a plurality of first and second access openings which respectively describe on the first metal layer a plurality of first and second solder bump pads, each of which is interconnected to at least one of the second solder bump pads. The sensing portion's photo-sensing die is positioned with its photo-sensing area opposing the front surface region of the assembly portion's substrate, and has formed thereon a plurality of solder bump pads electrically coupled to the photo-sensing area. Each of the first solder joints extends between one of the sensing portion's solder bump pads and one of the assembly portion's first solder bump pads.
Enhanced Reliability For Semiconductor Devices Using Dielectric Encasement
John J.H. Reche - Phoenix AZ, US Michael E. Johnson - Phoenix AZ, US Guy F. Burgess - Phoenix AZ, US Anthony P. Curtis - Phoenix AZ, US Stuart Lichtenthal - Phoenix AZ, US
Assignee:
FLIPCHIP INTERNATIONAL, LLC - Phoenix AZ
International Classification:
H01L 23/498 H01L 21/768
US Classification:
257738, 438615, 257E21589, 257E23069
Abstract:
A method and device for enhanced reliability for semiconductor devices using dielectric encasement is disclosed. The method and device are directed to improving the reliability of the solder joint that connects the integrated circuit (IC) chip to the substrate. The method comprises applying a layer of a photoimageable permanent dielectric material to a top surface of the semiconductor device, and patterning the layer of the photoimageable permanent dielectric material to have an opening over each feature. The method further comprises dispensing or stencil printing fluxing material into the permanent dielectric material openings, and applying solder, which contains no flux, to a top surface of the fluxing material. In one or more embodiments, the method further comprises heating the semiconductor device to a reflow temperature appropriate for the reflow of the solder, thereby causing the solder to conform to sidewalls of the permanent dielectric material openings to form a protective seal.
Laser Lithography For Integrated Circuit And Integrated Circuit Interconnect Manufacture
A laser lithography process for semiconductor interconnect and semiconductor manufacture having the advantages of non-contact printing processes and being much faster than prior art laser lithography processes is disclosed. In accordance with the process, a metal layer to be patterned either for use as a patterned metal layer or as a mask for patterning a layer therebelow, such as a think polyimide layer, is first coated with a very thin layer of polymer evaporated as a monomer using a vapor deposition process. This provides a very thin layer of polymer over the metal layer, which thin polymer layer is readily and quickly patterned by laser to provide a mask for the subsequent chemical etching of the metal layer. The vapor deposited polymer layer, while being very thin and thus readily removed by laser, is also substantially fault free, thereby providing a high-quality mask for the chemical etching process free of any possible damage from ordinary sources such as mask aligners, etc. , yet being readily removed when desired such as by way of example, by plasma etching thereof.