Cory J Reche

US Patent:

8312349, Nov 13, 2012

Filed:

Oct 27, 2009

Appl. No.:

12/606486

Inventors:

Cory Reche - Boise ID, US
Lee Nevill - Boise ID, US
Tim Martin - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 11/00

US Classification:

714773, 714 613

Abstract:

The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith.

US Patent:

8645749, Feb 4, 2014

Filed:

Feb 4, 2009

Appl. No.:

12/365816

Inventors:

Cory Reche - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 11/00

US Classification:

714 62, 714 61, 714 622, 714 611

Abstract:

Systems and methods are disclosed for storing the firmware and other data of a flash memory controller, such as using a RAID configuration across multiple flash memory devices or portions of a single memory device. In various embodiments, the firmware and other data used by a controller, and error correction information, such as parity information for RAID configuration, may be stored across multiple flash memory devices, multiple planes of a multi-plane flash memory device, or across multiple blocks or pages of a single flash memory device. The controller may detect the failure of a memory device or a portion thereof, and reconstruct the firmware and/or other data from the other memory devices or portions thereof.

US Patent:

20200004446, Jan 2, 2020

Filed:

Jun 29, 2018

Appl. No.:

16/024201

Inventors:

David Aaron Palmer - Boise ID, US
Cory J. Reche - Boise ID, US
Christopher Bueb - Folsom CA, US

International Classification:

G06F 3/06
G06F 12/02
G11C 16/20
G11C 11/56
G11C 8/12

Abstract:

Techniques are disclosed, including a method that can include entering a first mode of operation of an apparatus including a memory device, receiving first information indicative of a subsequent download of second information at the memory device, the memory device including a first group of cells configured as multi-level cell (MLC) memory, in response to receipt of the first information, converting a portion of the first group of cells from configuration as MLC memory to configuration as single-level cell (SLC) memory, receiving and storing the second information at the memory device, and upon exiting the first mode of operation, reconfiguring at least a portion of the SLC memory to MLC memory while simultaneously maintaining storage of the second information within the memory device.

US Patent:

20140149788, May 29, 2014

Filed:

Feb 3, 2014

Appl. No.:

14/171266

Inventors:

- Boise ID, US
Cory Reche - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 11/10

US Classification:

714 624

Abstract:

Systems and methods are disclosed for storing the firmware and other data of a flash memory controller, such as using a RAID configuration across multiple flash memory devices or portions of a single memory device. In various embodiments, the firmware and other data used by a controller, and error correction information, such as parity information for RAID configuration, may be stored across multiple flash memory devices, multiple planes of a multi-plane flash memory device, or across multiple blocks or pages of a single flash memory device. The controller may detect the failure of a memory device or a portion thereof, and reconstruct the firmware and/or other data from the other memory devices or portions thereof.