Haroon K Chaudhri

US Patent:

6851095, Feb 1, 2005

Filed:

Nov 24, 2001

Appl. No.:

09/999222

Inventors:

Arvind Srinivasan - San Jose CA, US
Haroon Chaudhri - Berkeley CA, US

Assignee:

Magma Design Automation, Inc. - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 4, 716 7, 703 13

Abstract:

A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. The technique accurately estimates of the performance (e. g. , transient delays) of an integrated circuit, and has fast execution times. The technique includes an incremental recharacterization feature where only portions of the design which have been changed or are new or different will need to be recharacterized during subsequent runs of the software. Portions of the design which are the same need not be recharacterized, and results for those portions from a previous run (stored in a database) are used. This saves execution time since the performance recharacterization or evaluation process is generally more time consuming than a database look up. The technique is applicable to small circuits having relatively few transistors, and especially well suited for integrated circuits having millions of transistors and components. The technique handles the effects of deep-submicron integrated circuit technology.

US Patent:

7000202, Feb 14, 2006

Filed:

Jun 29, 2004

Appl. No.:

10/881832

Inventors:

Arvind Srinivasan - San Jose CA, US
Haroon Chaudhri - Berkeley CA, US

Assignee:

Magma Design Automation, Inc. - Santa Clara CA

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716 4, 716 6

Abstract:

A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. Vectors are generated to estimate integrated circuit performance. The technique accurately estimates of the performance (e. g. , transient delays) of an integrated circuit, and has fast execution times. The technique is applicable to small circuits having relatively few transistors, and especially well suited for integrated circuits having millions of transistors and components. The technique handles the effects of deep-submicron integrated circuit technology.

US Patent:

7117461, Oct 3, 2006

Filed:

Jun 29, 2004

Appl. No.:

10/882003

Inventors:

Arvind Srinivasan - San Jose CA, US
Haroon Chaudhri - Berkeley CA, US

Assignee:

Magma Design Automation, Inc. - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716 4

Abstract:

A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. To estimate performance, the integrated circuit design is partitioned into strongly coupled components and state points are identified. The technique accurately estimates of the performance (e. g. , transient delays) of an integrated circuit, and has fast execution times. The technique is applicable to small circuits having relatively few transistors, and especially well suited for integrated circuits having millions of transistors and components. The technique handles the effects of deep-submicron integrated circuit technology.

US Patent:

7337416, Feb 26, 2008

Filed:

Jun 29, 2004

Appl. No.:

10/880649

Inventors:

Arvind Srinivasan - San Jose CA, US
Haroon Chaudhri - Berkeley CA, US

Assignee:

Magma Design Automation, Inc. - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 5

Abstract:

A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. When estimating performance, the invention partitions an integrated circuit into strongly coupled components. The technique accurately estimates of the performance (e. g. , transient delays) of an integrated circuit, and has fast execution times. The technique is applicable to small circuits having relatively few transistors, and especially well suited for integrated circuits having millions of transistors and components. The technique handles the effects of deep-submicron integrated circuit technology.

US Patent:

7340698, Mar 4, 2008

Filed:

Jun 29, 2004

Appl. No.:

10/881195

Inventors:

Arvind Srinivasan - San Jose CA, US
Haroon Chaudhri - Berkeley CA, US

Assignee:

Magma Design Automation, Inc. - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 5, 716 6, 716 8, 716 10, 703 13, 703 14, 703 15

Abstract:

A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. When simulating performance, scalars for transient performance are determined for strongly couple components. The technique accurately estimates of the performance (e. g. , transient delays) of an integrated circuit, and has fast execution times. The technique is applicable to small circuits having relatively few transistors, and especially well suited for integrated circuits having millions of transistors and components. The technique handles the effects of deep-submicron integrated circuit technology.

US Patent:

6499129, Dec 24, 2002

Filed:

Jul 21, 1999

Appl. No.:

09/357940

Inventors:

Arvind Srinivasan - San Jose CA
Haroon Chaudhri - Berkeley CA
Alexandre Zavorine - Campbell CA

Assignee:

Circuit Semantics, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

716 4, 716 7, 703 13

Abstract:

A technique to verify, evaluate, and estimate the performance of an integrated circuit is embodied in a computer software program that is executable by a computer system. The technique accurately estimates of the performance (e. g. , transient delays) of an integrated circuit, and has fast execution times. The technique is applicable to small circuits having relatively few transistors, and especially well suited for integrated circuits having millions of transistors and components. The technique handles the effects of deep-submicron integrated circuit technology.