Haotian Zhang from Arvada, CO, age 50

Resumes

Haotian Zhang

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Principal Asic System Architect

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Location:

1042 Albion Rd, Boulder, CO 80305

Industry:

Semiconductors

Work:

Broadcom
Principal Asic System Architect
Avago Technologies
Principal Asic System Architect
Lsi Corporation Aug 2008 - Jun 2010
Senior Staff Hardware Validation Engineer
Marvell Semiconductor Mar 2006 - Aug 2008
Senior Staff Asic System Architect
Maxtor Sep 2005 - Mar 2006
Senior Hdd Read Write Engineer

Education:

Carnegie Mellon University 2000 - 2005
Doctorates, Doctor of Philosophy, Computer Engineering, Philosophy Tsinghua University 2000 - 2000
Masters, Engineering Tsinghua University 1997 - 1997
Bachelors, Engineering 山东省实验中学 Shandong Experimental Senior High School

Skills:

Semiconductors
Debugging
Linux
System Architecture
C
Asic
C++
Testing
Verilog
Application Specific Integrated Circuits
Magnetic Read Channel
Serdes
Matlab

Interests:

Science and Technology

Us Patents

Systems And Methods For Low Latency Noise Cancellation
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US Patent:

8295001, Oct 23, 2012
Filed:

Sep 21, 2010
Appl. No.:

12/887369
Inventors:

Jingfeng Liu - Longmont CO, US
Haotian Zhang - Longmont CO, US
Hongwei Song - Longmont CO, US
George Mathew - San Jose CA, US
Assignee:

LSI Corporation - Milpitas CA
International Classification:

G11B 5/09
G11B 27/36
US Classification:

360 46, 360 31, 360 39
Abstract:

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes a data detector circuit, a detector mimicking circuit, and an error calculation circuit. The data detector circuit is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The data mimicking circuit is operable to process a second signal derived from the data input to yield a mimicked output. The error calculation circuit is operable to calculate a difference between the second signal and a third signal derived from the mimicked output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period.

Automatic Filter-Reset Mechanism
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US Patent:

8422609, Apr 16, 2013
Filed:

Sep 30, 2009
Appl. No.:

12/570326
Inventors:

Jingfeng Liu - Longmont CO, US
Haotian Zhang - Longmont CO, US
Hongwei Song - Longmont CO, US
Lingyan Sun - Longmont CO, US
Assignee:

LSI Corporation - San Jose CA
International Classification:

H04B 1/10
US Classification:

375350, 375232, 375267, 375349
Abstract:

In one embodiment, a (hard-drive) read channel has a (DFIR equalization) filter, whose tap coefficients are adaptively updated. A reset controller monitors an (LLR) signal generated downstream of the filter to automatically determine when to reset the filter, e. g. , by reloading an initial set of user-specified tap coefficients. For LLR values, the reset controller determines to reset the filter when the reset controller detects that too many recent LLR values have confidence values that are too low. When implemented in a hard-drive read channel, the reset controller can reset the filter one or more times during read operations within a sector of the hard drive.

Detector For High Frequency Amplitude Modulation Distortion
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US Patent:

8559283, Oct 15, 2013
Filed:

Aug 4, 2008
Appl. No.:

12/185643
Inventors:

Jingfeng Liu - Longmont CO, US
Haotian Zhang - Longmont CO, US
Assignee:

Marvell International Ltd. - Hamilton
International Classification:

G11B 7/00
US Classification:

369 4435
Abstract:

A signal corresponding to data read from an optical storage medium is equalized to generate an equalized signal. A signal level of the equalized signal is determined, and an expected signal level of the equalized signal without high frequency distortion is determined. A comparison between the signal level of the equalized signal and the expected signal level is performed, and an amplitude of the equalized signal is adjusted based on the comparison of the actual signal level of the equalized signal and the expected signal level. The equalized signal is decoded after adjusting the amplitude of the equalized signal.

Systems And Methods For Medium Contact Detection
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US Patent:

8630055, Jan 14, 2014
Filed:

Feb 22, 2011
Appl. No.:

13/031671
Inventors:

Jason S. Goldberg - Saint Paul MN, US
Jeffrey Grundvig - Loveland CO, US
Haotian Zhang - Longmont CO, US
Assignee:

LSI Corporation - San Jose CA
International Classification:

G11B 21/02
US Classification:

360 75, 360 31, 360 46, 360 7702
Abstract:

Various embodiments of the present invention provide systems and methods for detecting contact. For example, a method for detecting head contact is disclosed that includes: receiving an interface signal operable to indicate a physical contact between a sensing device and a storage medium; band pass filtering a data set derived from the interface signal to yield a band pass filtered output; comparing the band pass filtered output to a level threshold to yield a comparator output; summing the comparator output with at least one prior instance of the comparator output to yield an aggregated value; and comparing the aggregated value to an aggregate threshold to yield a contact output.

Systems And Methods For Semi-Independent Loop Processing
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US Patent:

20120068870, Mar 22, 2012
Filed:

Sep 21, 2010
Appl. No.:

12/887327
Inventors:

Jingfeng Liu - Longmont CO, US
Haotian Zhang - Longmont CO, US
Hongwei Song - Longmont CO, US
International Classification:

H03M 1/12
US Classification:

341155
Abstract:

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes an analog to digital converter circuit, a digital filter circuit, a data detector circuit, a mimic filter circuit, and a sample clock generation circuit. The analog to digital converter circuit is operable to receive a data input and to provide corresponding digital samples. The digital filter circuit is operable to receive the digital samples and to provide a filtered output. The data detector circuit is operable to perform a data detection process on the filtered output to yield a detected output. The mimic filter circuit is operable to receive the digital samples and to provide a mimicked output. The sample clock generation circuit is operable to provide a sample clock based at least in part on the detected output and the mimicked output.

Systems And Methods For Filter Constraint Estimation
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US Patent:

20120069891, Mar 22, 2012
Filed:

Sep 21, 2010
Appl. No.:

12/887330
Inventors:

Haotian Zhang - Longmont CO, US
Hongwei Song - Longmont CO, US
Jingfeng Liu - Longmont CO, US
Yu Liao - Longmont CO, US
International Classification:

H03K 5/159
US Classification:

375232
Abstract:

Various embodiments of the present invention provide systems and methods for calibrating a data processing circuit. For example, a method for calibrating a data processing circuit is discussed that includes providing a digital filter, providing a detector circuit, and providing an analog filter. Operation of the digital filter is at least in part governed by filter taps that correspond to a filter tap constraint value. Operation of the detector circuit is at least in part governed by a target parameter. Operation of the analog filter is at least in part governed by an analog parameter that is one of a plurality of analog parameters. The methods further include selecting a target parameter, and calculating the filter tap constraint value based on the target parameter. Combinations of the target parameter, the calculated filter tap constraint value, and each of the plurality of analog parameters are applied to identify the analog parameter.

Systems And Methods For Adc Sample Based Timing Recovery
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US Patent:

20120124454, May 17, 2012
Filed:

Nov 17, 2010
Appl. No.:

12/947962
Inventors:

Jingfeng Liu - Longmont CO, US
Hongwei Song - Longmont CO, US
Haotian Zhang - Longmont CO, US
International Classification:

G06F 11/07
US Classification:

714799, 714E11024
Abstract:

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes an analog to digital converter circuit operable to receive a data input and to provide corresponding digital samples, and a digital filter circuit operable to receive the digital samples and to provide a filtered output. A data detector circuit is operable to perform a data detection process on the filtered output to yield a detected output, and a phase detector circuit operable to calculate an error feedback value based at least in part on the detected output and the digital samples.

Read Channel With Oversampled Analog To Digital Conversion And Parallel Data Detectors
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US Patent:

20130050005, Feb 28, 2013
Filed:

Aug 23, 2011
Appl. No.:

13/215815
Inventors:

Jingfeng Liu - Longmont CO, US
Nayak Ratnakar Aravind - Allentown PA, US
Hongwei Song - Longmont CO, US
Haotian Zhang - Longmont CO, US
International Classification:

H03M 1/12
US Classification:

341155
Abstract:

Methods and apparatus are provided for processing a signal in a read channel using a selective oversampled analog to digital conversion. The disclosed selective oversampled analog to digital conversion simplifies the analog design by transferring at least a portion of the equalization and/or filtering processes to the digital domain. An oversampled analog to digital conversion is applied to an analog input signal to generate a plurality of digital samples for a given bit interval. The plurality of digital samples for a given bit interval are applied to a corresponding plurality of data detectors to obtain a detected output. The plurality of digital samples for a given bit interval may have a phase offset relative to one another. The detected output may be obtained, for example, by summing the outputs of the plurality of data detectors or by aggregating weighted outputs of the plurality of data detectors.