Frank J Malgioglio

US Patent:

8010922, Aug 30, 2011

Filed:

Feb 18, 2008

Appl. No.:

12/032762

Inventors:

Frank Malgioglio - Hopewell Junction NY, US
Adam R. Jatkowski - Wyoming PA, US
Brian A. Lasseter - Austin TX, US
Joseph J. Palumbo - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716114, 716113

Abstract:

Buffers are placed on selected nets coupled to input and output pins of entities in an IC device. This includes loading selected input and output pins of entities prior to respectively buffering nets of the entities and buffering in successive iterations, which includes setting artificial loads on selected input pins. The buffering in a current iteration is limited to i) buffering nets on the current iteration entity for receivers on the current iteration entity and ii) buffering nets on the current iteration entity directly coupled to respective nets of an immediately adjacent entity that has been buffered already in a preceding one of iterations, but only if the already buffered net is coupled to a receiver on its own net or a receiver on some other already buffered net via nets that have all been buffered via one or more of the preceding iterations.

US Patent:

8261224, Sep 4, 2012

Filed:

Feb 20, 2008

Appl. No.:

12/034644

Inventors:

Frank Malgioglio - Hopewell Junction NY, US
Christopher J. Berry - Hudson NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716122, 716118, 716119, 716123, 716132

Abstract:

Components are inserted into a cell-based current chin design with multiple levels of nested hierarchy. A selection of components having various silicon densities to insert into the current chip design is received. The components are inserted into the current chip design such that the components do not touch or overlap existing circuits or silicon shapes in the current chip design. The components are inserted such that components having highest silicon densities are placed further away from the existing circuits or silicon shapes than components having lower silicon densities.

US Patent:

60386266, Mar 14, 2000

Filed:

Mar 17, 1998

Appl. No.:

9/042971

Inventors:

Patrick James Meaney - Poughkeepsie NY
Frank Malgioglio - Hopewell Junction NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300
G06F 1340
G06F 1760
G06F 1100

US Classification:

710104

Abstract:

A scalable selector and method for a data processing system provides a multiple-bit, multiple bus selector logic for controling data routing and allowing dataflow to be connected and reconnected without change to control logic. The scalable selector logic includes a data selector controlled by the input controls as could accommodate controls from the Prior Art, as well providing an additional Orthogonality Checker to monitor for the condition where more than one control signal is active, and additional Data Valid logic to determine whether any of the input data buses has been selected to the output. The scalable selectors can be used in a switching network where these additional outputs operate as network controls allowing for the selection of buses in a switch network with orthogonality checking and data valid generation. The selectors also allow for swapping of data ports for timing and function sharing without impacting existing external control logic.

US Patent:

59960400, Nov 30, 1999

Filed:

Mar 17, 1998

Appl. No.:

9/042977

Inventors:

Patrick James Meaney - Poughkeepsie NY
Frank Malgioglio - Hopewell Junction NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300
G06F 1340
H04Q 1100

US Classification:

710131

Abstract:

A scalable selector and method for a data processing system provides a multiple-bit, multiple bus selector logic for controling data routing and allowing dataflow to be connected and reconnected without change to control logic. The scalable selector logic includes a data selector controlled by the input controls as could accommodate controls from the Prior Art, as well providing an additional Orthogonality Checker to monitor for the condition where more than one control signal is active, and additional Data Valid logic to determine whether any of the input data buses has been selected to the output. The scalable selectors can be used in a switching network where these additional outputs operate as network controls allowing for the selection of buses in a switch network with orthogonality checking and data valid generation. The selectors also allow for swapping of data ports for timing and function sharing without impacting existing external control logic.

US Patent:

20200004910, Jan 2, 2020

Filed:

Jun 29, 2018

Appl. No.:

16/023379

Inventors:

- Armonk NY, US
Frank Malgioglio - Hopewell Junction NY, US

International Classification:

G06F 17/50

Abstract:

Embodiments include method, systems and computer program products for designing physical devices using an iterative floorplan methodology. The method creating, using a processor, a rough floorplan, wherein the rough floorplan includes one or more tiles and estimates for one or more components associated with the floorplan. The processor converts the estimates for the one or more components to stresses and displacements/distortions associated with the one or more tiles. The processor further generates distortion data from the displacements/distortions associated with the one or more tiles. The processor further compares the distortion data to a threshold. The processor further creates a finalized floorplan based on the rough floorplan in response to the distortion data being below the threshold.

US Patent:

20180232481, Aug 16, 2018

Filed:

Feb 13, 2017

Appl. No.:

15/431061

Inventors:

- Armonk NY, US
Adam R. Jatkowski - Wyoming PA, US
Frank Malgioglio - Hopewell Junction NY, US
Ryan M. Nett - Austin TX, US
Joseph J. Palumbo - Poughkeepsie NY, US
Sean Salisbury - Poughkeepsie NY, US

International Classification:

G06F 17/50

Abstract:

A data processing system to implement wiring/silicon blockages via parameterized cells (pCells) includes a front end-of-line placement/blockage (FEOL P/B) controller to generate a placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC). The FEOL P/B outputs a placement blockage parameter that is stored in a wire track allocation database to indicate the placement blockage. A back end-of-line wiring track (BEOL WT) controller generates a wire track blockage of the IC. A BEOL power track (BEOL PT) controller generates a metal blockage within the wire track blockage. A combination of the metal blockage and the wire track blockage defines a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC.