Cymatics Laboratories Corp.
Chief Technology Officer and Ceo, Co-Founder
Renaissance Wireless Corp Jul 2005 - Feb 2009
Director, Product Development
Cadence Design Systems Nov 2004 - Jun 2005
Senior Product Engineer
Ic Mechanics 2001 - Nov 2004
Vice President Engineering
Pcb Piezotronics Jul 1991 - Aug 1993
Design Engineer
Education:
Carnegie Mellon University 1993 - 2001
Doctorates, Doctor of Philosophy, Electrical Engineering
University at Buffalo 1991 - 1993
Master of Science, Masters, Electrical Engineering
Insa Rennes 1986 - 1991
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Ic Semiconductors Sensors Mixed Signal Analog Mems Electronics Asic Analog Circuit Design Rf Soc Eda Digital Signal Processors Product Development Circuit Design Engineering Management Integrated Circuit Design Hardware Architecture Analog Design System on A Chip Integrated Circuits Application Specific Integrated Circuits
Us Patents
Direct Digital Synthesizer For Reference Frequency Generation
Anthony L. Tsangaropoulos - San Carlos CA, US David Francois Guillou - Pittsburgh PA, US
Assignee:
Cymatics Laboratories Corp. - Pittsburgh PA
International Classification:
H03L 7/00
US Classification:
331 34
Abstract:
A direct digital frequency synthesizer having a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The multi-modulus divider receives an input clock having an input pulse frequency fand outputs some integer fraction of those pulses at an instantaneous frequency fthat is some integer fraction (1/P) of the input frequency. The multi-modulus divider selects between at least two ratios of P (1/P or 1/P+1) in response to a signal from the numerically controlled oscillator. The numerically controlled oscillator receives a value which is the accumulator increment (i.e. the number of divided pulse edges) required before an overflow occurs that causes the multi-modulus divider to change divider ratios in response to receiving an overflow signal. The numerically controlled oscillator also outputs both the overflow signal and a delay signal to the delay generator. The delay signal contains phase-dithering noise that is induced by input into the accumulator of an increment generated from a pseudo-random noise generator. The delay signal further controls the frequency of the multi-modulus divider output signal (V) to provide an output signal (V) with an fthat has improved phase and timing jitter performance over prior art direct digital frequency synthesizer architectures.
Rajarishi Sinha - Pittsburgh PA, US David Francois Guillou - Pittsburgh PA, US
Assignee:
CYMATICS LABORATORIES CORP. - Pittsburgh PA
International Classification:
H02N 1/00
US Classification:
310300
Abstract:
A MEMS or NEMS device with at least one component made of a non-naturally occurring isotope material. The refined isotopic material provides advantages to device operation such as reduced mechanical loss, increased breakdown voltage, improved tunability and other advantages.
Direct Digital Synthesizer For Reference Frequency Generation
Anthony L. Tsangaropoulos - San Carlos CA, US David Francois Guillou - Pittsburgh PA, US
Assignee:
Cymatics Laboratories Corp. - Pittsburgh PA
International Classification:
H03K 21/00
US Classification:
327115
Abstract:
A direct digital frequency synthesizer includes a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The divider receives an input clock having an input pulse frequency and outputs some integer fraction of those pulses at an instantaneous frequency that is some integer fraction (1/P) of the input frequency. The divider selects between at least two ratios of P (1/P or 1/P+1) in response to a signal from the oscillator. The oscillator receives a value which is the accumulator increment (i.e. the number of divided pulse edges) required before an overflow occurs that causes the divider to change divider ratios in response to receiving an overflow signal. The oscillator also outputs both the overflow signal and a delay signal to the delay generator. The delay signal contains phase-dithering noise that is induced by input into the accumulator of an increment generated from a pseudo-random noise generator.
- PITTSBURGH PA, US David Francois Guillou - Pittsburgh PA, US
Assignee:
CYMATICS LABORATORIES CORP. - Pittsburgh PA
International Classification:
H01L 41/08 H01L 41/39 H03H 3/04 H01L 21/66
US Classification:
310346, 438 14
Abstract:
A resonator device comprising a piezoelectric material and at least one electrode, the device also provided with a material with a positive coefficient of stiffness, wherein the material is disposed in the device as an electrode or as a separate layer adjacent the piezoelectric material formed as one or more layers in the device. The material that performs the temperature compensating function is selected from the group consisting of ferromagnetic metal alloys, shape-memory metal alloys, and polymers, wherein the selected material has a temperature coefficient that varies with the relative amounts of the individual constituents of the compositions and wherein the composition is selected to provide the material with the positive coefficient of stiffness.
- Pittsburgh PA, US David Francois Guillou - Pittsburgh PA, US
Assignee:
CYMATICS LABORATORIES CORP. - Pittsburgh PA
International Classification:
H03B 28/00
US Classification:
331 48
Abstract:
An integrated circuit device for generating an output frequency includes a master oscillator and a slave oscillator formed on an integrated circuit substrate. The master oscillator utilizes a bulk acoustic wave resonator that provides a reference frequency source to the device. The frequency of the slave oscillator is periodically adjusted with respect to the reference frequency source and provided as an output. The master oscillator is periodically enabled to adjust the slave oscillator. Additional automatic temperature compensation is enabled as necessary.