Carl W Moreland

Author:

Carl Moreland

ISBN #:

0714829544

Author:

Carl Moreland

ISBN #:

0714880647

US Patent:

6686864, Feb 3, 2004

Filed:

Aug 28, 2002

Appl. No.:

10/229039

Inventors:

Carl W. Moreland - Oak Ridge NC

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 138

US Classification:

341161, 341155

Abstract:

Pipelined ADC systems are provided with gain-matching structures that substantially eliminate gain errors between preceding and succeeding converter stages. These structures include reference signal-conditioning elements which mimic at least one of main signal-conditioning elements in the succeeding converter stages. The reference signal-conditioning elements control reference signals which maintain a match between the full-scale range of a digital-to-analog converter (DAC) in a succeeding stage and the âgained-upâ step size of a DAC in a preceding stage. This match substantially eliminates the gain errors.

US Patent:

6753732, Jun 22, 2004

Filed:

Feb 10, 2003

Appl. No.:

10/364163

Inventors:

Carl W. Moreland - Oak Ridge NC

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03F 345

US Classification:

330261, 330285

Abstract:

Variable-gain amplifiers (VGAs) are provided that realize gain accuracy (e. g. , over variations in temperature and fabrication processes) while also providing this accuracy over a wide bandwidth and without the signal-to-noise degradation typically associated with signal attentuating elements. Differential signal and gain amplifiers of these VGAs include current sources which are controlled by a common error signal S. The gain amplifier is supplemented by feedback structure that generates the error signal S and controls the amplifiers transconductance to be the ratio of at least one of currents and resistors. Because such ratios can be well matched (especially in integrated circuit realizations of the variable-gain amplifiers) and because the current source of the signal amplifier is also controlled by the error signal S , this wide-band, low-noise open-loop amplifiers gain is accurately controlled.

US Patent:

6822519, Nov 23, 2004

Filed:

Feb 10, 2003

Appl. No.:

10/364162

Inventors:

Carl W. Moreland - Oak Ridge NC
Bryan S. Puckett - Stokesdale NC

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03L 700

US Classification:

331 16, 531 1 A, 531 17, 531 25, 531 14, 531177 V

Abstract:

Synthesizer structures and alignment methods are provided that facilitate quadrature demodulation. The structures are realized with phase-locked loops that include half-rate frequency dividers to provide loop output signals with a wide range of output frequencies and with frequency dividers that provide quadrature signals in response to the output signals. The structures include controllers that direct alignment methods which lock a VCO to a reference signal from a reference frequency divider to thereby provide the output signals.

US Patent:

61632902, Dec 19, 2000

Filed:

Jul 13, 1999

Appl. No.:

9/352829

Inventors:

Carl W. Moreland - Oak Ridge NC
Michael R. Elliott - Greensboro NC

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 112

US Classification:

341155

Abstract:

Linearized unity-gain folding amplifiers include first and second differential pairs of transistors that have offset voltages between control terminals and first current terminals. The control terminals are differentially coupled through input paths to a differential input port and the joined first current terminals receive respective first and second currents through respective first and second level-shift resistors. Thus, folded and level-shifted signals can be differentially coupled via output paths between the first and second level-shift resistors and an output port. For each of the differential pairs, at least one correction voltage is generated to substantially match the offset voltage of one of the transistors of that differential pair when a differential input voltage has one polarity and the offset voltage of another of the transistors when the differential input voltage has a different polarity. The correction voltage is inserted in one of the input paths in a feedback mode of the invention and in one of the output paths in a feed-forward mode and the correction voltage is oriented to correct variations in the offset voltages of one of the differential pairs that occur adjacent a polarity transition of the differential input voltage. In serial arrangements of these amplifiers, their high linearity enhances the quantization processes of successive stages so that longer serial arrangements can be reliably used.

US Patent:

55393381, Jul 23, 1996

Filed:

Dec 1, 1994

Appl. No.:

8/348052

Inventors:

Carl W. Moreland - Greensboro NC

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03K 519

US Classification:

327 19

Abstract:

A circuit for selecting between two states and using the same pin as an input and an output. On power-up, the pin can be connected to either a grounded resistor (to select the first state) or the power supply (to select the second state). The input signal generates a logic select signal. The logic select signal selects between first and second logic formats. If the first format is selected, the pin is used to output a reference voltage for that format. If the second format is selected, the logic select signal also provides a disable signal, that prevents the reference voltage output from appearing on the pin.

US Patent:

61916196, Feb 20, 2001

Filed:

Aug 24, 1999

Appl. No.:

9/382046

Inventors:

Carl W. Moreland - Oak Ridge NC
Michael R. Elliott - Greensboro NC

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03K 19086

US Classification:

326126

Abstract:

High-speed signal translators are provided to convert differential input signals (e. g. , ECL signals) to single-ended output signals (e. g. , CMOS signals). An exemplary translator is formed with first and second current mirrors, first and second complimentary differential pairs of transistors, a complimentary transistor output stage and first and second current-diverting transistors. The complimentary output stage initially generates the single-ended output signal in response to currents received from the complimentary differential pairs. When the output signal has been established, the current-diverting transistors respond by carrying at least portions of the currents supplied by the complimentary differential pairs. The current-diverting transistors also drive the current mirrors to divert other portions of these currents away from the complimentary output stage. Stored charges in the output stage are accordingly reduced and its response time enhanced.

US Patent:

62949020, Sep 25, 2001

Filed:

Aug 11, 2000

Appl. No.:

9/637807

Inventors:

Carl W. Moreland - Oak Ridge NC
Marvin J. Young - Greensboro NC

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G05F 140
G05F 320

US Classification:

323268

Abstract:

A bandgap reference circuit provides an output reference voltage that is generally insensitive to fluctuations in supply voltage, ambient temperature, and output load current. A current regulator establishes an output whose variations are reduced, preferably logarithmically, relative to variations in a supply voltage. A bandgap generator fed by the output current provides an output reference voltage with similarly suppressed variations. A control amplifier biases the bandgap generator to provide a high level common-mode rejection of various error sources.

US Patent:

56844190, Nov 4, 1997

Filed:

Dec 1, 1994

Appl. No.:

8/347909

Inventors:

Frank Murden - Greensboro NC
Carl W. Moreland - Greensboro NC

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 112
H03M 146

US Classification:

327104

Abstract:

A serial-type A/D converter uses magnitude amplifiers("magamps") and comparators for effecting the conversion of analog signals to Gray scale code signals that are then converted to binary digital signals by a Gray scale code-to-binary portion of the serial-type A/D converter. More specifically, a serial-type A/D converter uses an n-bit converter that has n-1 magamps and n-comparators. The n-1 magamps are cascaded such that the V. sub. OL and V. sub. OH outputs of a stage are the inputs to the next stage. The output of the comparators are input to the Gray scale code-to-binary portion of the serial A/D converter. The latching of the comparators occurs outside of the magamps. This allows for the parallel latching of the n comparators. The speed of the serial-type A/D converter is determined by the bandwidth of the magamps. The serial-type A/D converter includes an offset method that significantly reduces the effects of early voltage, V. sub.