Yashwant K Malaiya

US Patent:

57578168, May 26, 1998

Filed:

Oct 24, 1996

Appl. No.:

8/736623

Inventors:

Waleed K. Al-Assadi - Austin TX
Yashwant K. Malaiya - Fort Collins CO

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

G06F 1100

US Classification:

371 211

Abstract:

An integrated circuit includes a circuit architecture that enhances the I. sub. DDQ testability of circuitry such as random access memories. Increased accuracy and test speed are achieved by partitioning the circuit array into multiple partitions. Pairs of partitions connected to a voltage source node and having substantially identical ground line capacitances are subdivided into respective blocks. Each block in a pair of the partitions includes a corresponding block in the other partition. Each of the corresponding blocks in a pair has a substantially equal ground line capacitance, and preferably each of the blocks has a substantially equal ground line capacitance. Pairs of corresponding blocks are coupled to respective built-in current comparators. Each block is preferably configured to include portions of non-contiguous, interleaved bit line segments and portions of non-contiguous, interleaved word lines. Simultaneous test vector corresponding block write operations followed by simultaneous read operations detect a multitude of I. sub.

Author:

Yashwant K. Malaiya

ISBN #:

0818621109

Author:

Yashwant K. Malaiya

ISBN #:

0818632151

Author:

Yashwant K. Malaiya

ISBN #:

0818691107

Author:

Yashwant K. Malaiya

ISBN #:

0818691913

Author:

Yashwant K. Malaiya

ISBN #:

0769506372