Yanqing Q Wu from 7504 Abby Marle E, Lafayette, IN 47906, age 42

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Circuit Including A Negative Differential Resistance (Ndr) Device Having A Graphene Channel, And Method Of Operating The Circuit
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US Patent:

8593180, Nov 26, 2013
Filed:

Mar 12, 2012
Appl. No.:

13/418066
Inventors:

Shu-Jen Han - Cortlandt Manor NY, US
Yu-Ming Lin - West Harrison NY, US
Yanqing Wu - Ossining NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H03K 19/02
US Classification:

326135, 977734
Abstract:

A circuit includes a negative differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source which modulates a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance.

Inp-Based Transistor Fabrication
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US Patent:

20090042344, Feb 12, 2009
Filed:

Jun 13, 2008
Appl. No.:

12/139010
Inventors:

Peide Ye - West Lafayette IN, US
Zhiyuan Cheng - Lincoln MA, US
Yi Xuan - West Lafayette IN, US
Yanqing Wu - West Lafayette IN, US
Bunmi Adekore - Medford MA, US
James Fiorenza - Wilmington MA, US
Assignee:

AmberWave Systems Corporation - Salem NH
Purdue Research Foundation - West Lafayette IN
International Classification:

H01L 21/335
H01L 21/336
US Classification:

438172, 438285, 257E21409, 257E21403
Abstract:

Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

Graphene Devices And Semiconductor Field Effect Transistors In 3D Hybrid Integrated Circuits
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US Patent:

20120181510, Jul 19, 2012
Filed:

Jan 18, 2012
Appl. No.:

13/352737
Inventors:

Phaedon Avouris - Yorktown Heights NY, US
Yanqing Wu - Ossining NY, US
Wenjuan Zhu - Fishkill NY, US
Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:

H01L 27/088
H01L 21/336
H01L 21/28
B82Y 40/00
B82Y 99/00
US Classification:

257 29, 438152, 438675, 257347, 438285, 977734, 257E2706, 257E21409, 257E21158
Abstract:

A three-dimensional integrated circuit includes a semiconductor device, an insulator formed on the semiconductor device, an interconnect formed in the insulator, and a graphene device formed on the insulator.

Inp-Based Transistor Fabrication
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US Patent:

20130040431, Feb 14, 2013
Filed:

Oct 18, 2012
Appl. No.:

13/654531
Inventors:

Taiwan Semiconductor Manufacturing Company - Hsin-Chu, TW
Zhiyuan Cheng - Lincoln MA, US
Yi Xuan - West Lafayette IN, US
Yanqing Wu - West Lafayette IN, US
Bunmi Adekore - Medford MA, US
James Fiorenza - Wilmington MA, US
Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. - Hsin-Chu
International Classification:

H01L 21/336
H01L 21/283
US Classification:

438285, 438585, 257E21409, 257E2119
Abstract:

Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

Graphene Pressure Sensors
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US Patent:

20130270511, Oct 17, 2013
Filed:

Apr 12, 2012
Appl. No.:

13/445029
Inventors:

Jin Cai - Cortlandt Manor NY, US
Yanqing Wu - Ossining NY, US
Wenjuan Zhu - Fishkill NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 29/06
H01L 21/02
B82Y 40/00
US Classification:

257 9, 438 50, 257E29005, 257E21002, 977734
Abstract:

Semiconductor nano pressure sensor devices having graphene membrane suspended over cavities formed in a semiconductor substrate. A suspended graphene membrane serves as an active electro-mechanical membrane for sensing pressure, which can be made very thin, from about one atomic layer to about 10 atomic layers in thickness, to improve the sensitivity and reliability of a semiconductor pressure sensor device.

Graphene Pressure Sensors
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US Patent:

20130273682, Oct 17, 2013
Filed:

Aug 31, 2012
Appl. No.:

13/600469
Inventors:

Jin Cai - Cortlandt Manor NY, US
Yanqing Wu - Ossining NY, US
Wenjuan Zhu - Fishkill NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 29/02
US Classification:

438 50, 257E29002
Abstract:

Semiconductor nano pressure sensor devices having graphene membrane suspended over open cavities formed in a semiconductor substrate. A suspended graphene membrane serves as an active electro-mechanical membrane for sensing pressure, which can be made very thin, from about one atomic layer to about 10 atomic layers in thickness, to improve the sensitivity and reliability of a semiconductor pressure sensor device.

Inp-Based Transistor Fabrication
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US Patent:

20180019320, Jan 18, 2018
Filed:

Sep 1, 2017
Appl. No.:

15/694375
Inventors:

- Hsinchu, TW
- WEST LAFAYETTE IN, US
Yi Xuan - West Lafayette IN, US
Yanqing Wu - West Lafayette IN, US
Bunmi Adekore - Medford MA, US
James Fiorenza - Wilmington MA, US
International Classification:

H01L 29/66
H01L 29/51
H01L 21/28
H01L 29/778
H01L 21/02
Abstract:

Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device are disclosed. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.