Victoria Lee Meier

US Patent:

6732343, May 4, 2004

Filed:

May 13, 2002

Appl. No.:

10/144117

Inventors:

Troy Horst Frerichs - Fort Collins CO
Ryan Matthew Korzyniowski - Fort Collins CO
Victoria Meier - Ft Collins CO

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

G06F 1750

US Classification:

716 10, 716 1, 716 2, 716 8, 716 9, 716 12

Abstract:

A clock buffer placement system and method are provided for the placement of clock buffers in a datapath stack. In accordance with one aspect of the invention, the system positions at least one track beside the datapath stack in a netlist, and identifies placement of clock buffers needed in the at least one track. Then, the system modifies the netlist by connecting at least one datapath macro to the clock buffers on the at least one track. In accordance with another aspect of the invention, a method includes positioning at least one track beside the datapath stack in a netlist, and identifying placement of clock buffers needed in the at least one track. Then, the netlist is modified by connecting at least one datapath macro to the clock buffers on the at least one track.

US Patent:

6894535, May 17, 2005

Filed:

Dec 18, 2001

Appl. No.:

10/025353

Inventors:

Jeffrey Thomas Robertson - Wellington CO, US
Victoria Meier - Ft Collins CO, US
Paul D Nuber - Ft Collins CO, US

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

H03K019/173

US Classification:

326 46, 326 56

Abstract:

At least one column of a latch array includes a tri-state buffer in the upper portion of the column that receives the output of the uppermost group of latches of the column as its input, and which is enabled by a dump signal when a latch in the upper portion is addressed. When the dump signal that triggers the tri-state buffer is active, whatever is at the input of the tri-state buffer is driven by the buffer to the bottom of the latch array column, thereby providing the driven signal with sufficient strength to obviate transition timing and signal integrity problems. When the dump signal that triggers the tri-state buffer is not asserted, the tri-state buffer output exhibits high impedance, which isolates the lower portion of the latch array column from the upper portion of the latch array column, thereby preventing the capacitance associated with the line connecting the tri-state buffer to the output of the uppermost latch from affecting the driving ability of the latches in the lower portion of the column.

US Patent:

6910194, Jun 21, 2005

Filed:

Jul 19, 2002

Appl. No.:

10/199137

Inventors:

David James Mielke - Fort Collins CO, US
Victoria Meier - Ft Collins CO, US

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

G06F017/50

US Classification:

716 6, 716 4

Abstract:

Systems and methods for timing a linear data path element within an integrated circuit design are provided. A representative system includes a computer and a memory element associated with the computer. The computer includes logic for receiving information describing the integrated circuit design. The integrated circuit design includes a description of a signal-timing path and the clock distribution system across the integrated circuit. The memory is configured with executable steps to generate a model of a signal that traverses a signal-timing path that is coupled to a linear element. The model includes a mechanism for simulating clock signal operation over a plurality of clock distribution structure types. A representative method includes the following steps: acquiring circuit information; identifying a signal path within the circuit information; recognizing when the signal-timing path is coupled to a linear element; associating a clock uncertainty with the clock signal; determining a confidence interval for the signal-timing path responsive to the recognizing step, wherein the clock signal is propagated along the signal-timing path; and associating the confidence interval with the signal-timing path.

US Patent:

6948148, Sep 20, 2005

Filed:

Feb 5, 2002

Appl. No.:

10/068649

Inventors:

Victoria Meier - Ft Collins CO, US
William C Borough - Fort Collins CO, US
Jeffrey Thomas Robertson - Wellington CO, US

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

G06F017/50

US Classification:

716 18, 716 11, 716 14

Abstract:

Generating a data path macro cell based upon a text format template comprising variables. The system provides for creating a text format template by generating a text format representation of a data path macro cell based upon data representing a graphical layout of the data path macro cell. Variables are substituted for constants. Variables are changed to values associated with a macro cell having desired characteristics to create a text format file representative of a desired macro cell. Graphical data representing the layout of a macro cell is generated based upon the text format file.

US Patent:

20030107396, Jun 12, 2003

Filed:

Dec 12, 2001

Appl. No.:

10/020366

Inventors:

Victoria Meier - Fort Collins CO, US
Paul Nuber - Fort Collins CO, US

International Classification:

H03K019/173

US Classification:

326/037000

Abstract:

Localizing bypass capacitance for the purpose of reducing or eliminating noise in power supplies in an integrated circuit (IC). After a data path block of macro cells has been constructed by the IC designer, a determination is made as to which cells of the macro cells comprise functionality that will not be used by the IC when it is operating. At least a plurality of cells that are determined to be cells that comprise functionality that will not be used when the IC is operating are filled with bypass capacitors. Because there are typically a large number of cells that will not be used when the IC is operating, filling a plurality or all of these cells with bypass capacitors ensures that bypass capacitors will be located in close proximity to power supplies on the IC, which ensures that the bypass capacitors will be effective at reducing or eliminating noise in the power supplies.