Vickie Y Wu

US Patent:

20130235239, Sep 12, 2013

Filed:

Feb 27, 2013

Appl. No.:

13/778859

Inventors:

- George Town, KY
Vickie Wu - Cupertino CA, US

Assignee:

Aptina Imaging Corporation - George Town

International Classification:

H04N 5/232

US Classification:

348302, 348372

Abstract:

Power saving techniques are provided for processing circuitry on image sensors. Processing circuitry may include one or more processing blocks. The processing blocks may receive pixel data in the form of lines separated by blanking time. To reduce power consumption, each processing block may have a clock that is enabled when processing data and disabled during blanking time. The processing blocks may have respective clocks that are enabled and disabled at different times. Timing control circuitry may provide a clock enable signal to a first processing block. Each processing block may receive a clock enable signal and output a time-shifted clock enable signal for a subsequent processing block.

US Patent:

7493543, Feb 17, 2009

Filed:

Jul 20, 2006

Appl. No.:

11/490669

Inventors:

Vickie Wu - Cupertino CA, US
Arnold Louie - Cupertino CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

G06F 11/00
G01R 31/28

US Classification:

714738, 714725, 714736

Abstract:

Method and system for testing an integrated circuit and more particularly, for determining timing associated with an input or output of an embedded circuit, in an integrated circuit for testing are described. A bit is adjustably delayed with a first adjustable delay to provide a delayed bit. The delayed bit is provided to a bus, such as an input bus for example, of the embedded circuit as a second vector. A third vector is output from the embedded circuit responsive to the second vector. A fourth vector is obtained having second multiple bits. The fourth vector is compared with the third vector to determine a period of delay associated with at least approximately a maximum operating frequency of the embedded circuit.

US Patent:

20220207783, Jun 30, 2022

Filed:

Dec 30, 2020

Appl. No.:

17/138817

Inventors:

- Santa Clara CA, US
- Markham, CA
King Chiu Tam - Markham, CA
Shilpa Rajagopalan - Markham, CA
Benjamin Koon Pan Chan - Markham, CA
Vickie Youmin Wu - Santa Clara CA, US

Assignee:

Advanced Micro Devices, Inc. - Santa Clara CA
ATI Technologies ULC - Markham

International Classification:

G06T 9/00
G06T 3/40
G06N 3/02

Abstract:

Methods and devices are provided for processing image data on a sub-frame portion basis using layers of a convolutional neural network. The processing device comprises memory and a processor. The processor is configured to receive frames of image data comprising sub-frame portions, schedule a first sub-frame portion of a first frame to be processed by a first layer of the convolutional neural network when the first sub-frame portion is available for processing, process the first sub-frame portion by the first layer and continue the processing of the first sub-frame portion by the first layer when it is determined that there is sufficient image data available for the first layer to continue processing of the first sub-frame portion. Processing on a sub-frame portion basis continues for subsequent layers such that processing by a layer can begin as soon as sufficient data is available for the layer.