Thomas Allan Kocian

US Patent:

6762868, Jul 13, 2004

Filed:

Nov 9, 2001

Appl. No.:

09/990952

Inventors:

Jwei Wien Liu - Plano TX
Thomas A. Kocian - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G02B 2600

US Classification:

359237, 359290

Abstract:

A drop-in aperture , which improves the performance and lowers the cost of electro-optical SLM packages. The disclosed package provides a separate metal light shield (aperture) and antireflective coated cover , and positions the aperture inside the package in close proximity to the SLMs surface. This approach further uses an on-chip SLM light shield to define the projected screen border, thereby making the edge definition of the metal drop-in aperture less critical. Therefore, the cover can be mounted well away from the plane of the SLM, which relaxes the defect requirements of the cover and lowers the cost of the overall package. The package of this invention improves the performance and lifetime and lowers the cost of projection display systems.

US Patent:

6908791, Jun 21, 2005

Filed:

Apr 29, 2002

Appl. No.:

10/135559

Inventors:

Thomas A. Kocian - Dallas TX, US
Richard L. Knipe - McKinney TX, US
Mark H. Strumpell - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L021/48
H01L021/50

US Classification:

438110, 438116, 438118

Abstract:

A method and system in which a semiconductor wafer having a plurality of dies is inspected through a visual inspection and/or an electrical test. If certain of the dies on the wafer pass the inspection, then windows are mounted or affixed above those certain dies while they are still a part of the wafer.

US Patent:

7226810, Jun 5, 2007

Filed:

Jun 20, 2005

Appl. No.:

11/157024

Inventors:

Thomas A. Kocian - Dallas TX, US
Richard L. Knipe - McKinney TX, US
Mark H. Strumpell - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/50
H01L 21/46

US Classification:

438110, 438113, 438460, 257E21499

Abstract:

A method and system in which a semiconductor wafer having a plurality of dies is inspected through a visual inspection and/or an electrical test. If certain of the dies on the wafer pass the inspection, then windows are mounted or affixed above those certain dies while they are still a part of the wafer.

US Patent:

7466018, Dec 16, 2008

Filed:

Jun 4, 2007

Appl. No.:

11/757546

Inventors:

Thomas A. Kocian - Dallas TX, US
Richard L. Knipe - McKinney TX, US
Mark H. Strumpell - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/02
H01L 23/12

US Classification:

257680, 257704, 257E23124, 257E23127

Abstract:

A method and system in which a semiconductor wafer having a plurality of dies is inspected through a visual inspection and/or an electrical test. If certain of the dies on the wafer pass the inspection, then windows are mounted or affixed above those certain dies while they are still a part of the wafer.

US Patent:

8608894, Dec 17, 2013

Filed:

Nov 17, 2011

Appl. No.:

13/298955

Inventors:

Stephen H. Black - Buellton CA, US
Thomas A. Kocian - Dallas TX, US

Assignee:

Raytheon Company - Waltham MA

International Classification:

G01J 1/04

US Classification:

156280, 2503384

Abstract:

A method for manufacturing a wafer level packaged focal plane array, in accordance with certain embodiments, includes forming a detector wafer, which may include forming detector arrays and read-out circuits. The method may also include forming a lid wafer. Forming the lid wafer may include polishing a surface of a magnetically confined Czochralski (MCZ) wafer, bonding a Czochralski wafer to the MCZ wafer, and forming pockets in the Czochralski wafer. Each pocked may expose a portion of the polished surface of the MCZ wafer. The method may further include bonding the lid wafer and the detector wafer together such that the each detector array and read-out circuit are sealed within a different pocket, thereby forming a plurality of wafer level packaged focal plane arrays. The method may additionally include separating at least one wafer level packaged focal plan array from the plurality of wafer level packaged focal plane arrays.

US Patent:

20120096813, Apr 26, 2012

Filed:

Oct 18, 2011

Appl. No.:

13/275635

Inventors:

Roland W. Gooch - Dallas TX, US
Stephen H. Black - Buellton CA, US
Thomas A. Kocian - Dallas TX, US
Buu Diep - Murphy TX, US

Assignee:

Raytheon Company - Waltham MA

International Classification:

B65B 3/02

US Classification:

53452

Abstract:

In accordance with particular embodiments, a method for packaging an incident radiation detector includes depositing an opaque solder resistant material on a first surface of a transparent lid substrate configured to cover at least one detector. The method also includes forming at least one cavity in the lid substrate. The method further includes forming a first portion of at least one hermetic seal ring on the opaque solder resistant material. The first portion of each hermetic seal ring surrounds a perimeter of a corresponding cavity in the lid substrate. The method also includes aligning the first portion of the at least one hermetic seal ring with a second portion of the at least one hermetic seal ring. The method additionally includes bonding the first portion of the at least one hermetic seal ring with the second portion of the at least one hermetic seal ring with solder.

US Patent:

20120111925, May 10, 2012

Filed:

Sep 13, 2011

Appl. No.:

13/231749

Inventors:

Buu Diep - Murphy TX, US
Thomas A. Kocian - Dallas TX, US
Roland W. Gooch - Dallas TX, US

Assignee:

Raytheon Company - Waltham MA

International Classification:

B23K 31/02
B23K 1/20
B23K 3/06
B23K 3/08

US Classification:

228178, 228 51, 228205, 228 18

Abstract:

In certain embodiments, a system includes a deposition system and a plasma/bonding system. The deposition system deposits a solder outwardly from a substrate of a number of substrates. The plasma/bonding system comprises a plasma system configured to plasma clean the substrate and a bonding system configured to bond the substrates. The plasma/bonding system at least reduces reoxidation of the solder. In certain embodiments, a method comprises depositing solder outwardly from a substrate, removing metal oxide from the substrate, and depositing a capping layer outwardly from the substrate to at least reduce reoxidation of the solder.

US Patent:

20120127579, May 24, 2012

Filed:

Nov 21, 2011

Appl. No.:

13/300947

Inventors:

Stephen H. Black - Buellton CA, US
Thomas A. Kocian - Dallas TX, US
Buu Q. Diep - Murphy TX, US

Assignee:

Raytheon Company - Waltham MA

International Classification:

G02B 1/11
B32B 37/14

US Classification:

359601, 156 60

Abstract:

According to one embodiment, a method includes receiving a light beam at an anti-reflective layer of optically transmissive material. The anti-reflective layer has an outer surface disposed within a recess of a protective layer of optically transmissive material, such that the outer surface is protected by the recess and the protective layer from being contacted. The outer surface is further disposed along an optical path of an optical device disposed inwardly from the outer surface. The anti-reflective layer has an average cross-sectional thickness that is less than an average cross-sectional thickness of the protective layer. The method further includes modulating the light beam using the anti-reflective layer.