Thomas J Bucelot

US Patent:

20130049827, Feb 28, 2013

Filed:

Aug 25, 2011

Appl. No.:

13/217335

Inventors:

THOMAS J. BUCELOT - WAPPINGERS FALLS NY, US
PHILLIP J. RESTLE - KATONAH NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

H03L 7/00

US Classification:

327144

Abstract:

There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. On each of the two or more strata, the clock distribution network includes a clock grid having a plurality of sectors for providing the global clock signals to various chip locations, a multiple-level buffered clock tree for driving the clock grid and including at least a root and a plurality of clock buffers, and one or more multiplexers for providing the global clock signals to at least a portion of the buffered clock tree. Inputs of at least some of the plurality of clock buffers on each of the two or more strata are shorted together using chip-to-chip interconnects to reduce skewing of the global clock signals with respect to the various chip locations.

US Patent:

20160105177, Apr 14, 2016

Filed:

Dec 17, 2015

Appl. No.:

14/973363

Inventors:

- Armonk NY, US
THOMAS J. BUCELOT - WAPPINGERS FALLS NY, US
ALAN J. DRAKE - ROUND ROCK TX, US
PHILLIP J. RESTLE - KATONAH NY, US
DAVID W. SHAN - Austin TX, US
MRIGANK SHARAD - WEST LAFAYETTE IN, US

International Classification:

H03K 19/00
H03K 5/135

Abstract:

A clock driver is provided. The clock driver includes a multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving branch, and an output. The input is for receiving an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. The output is connected to the positive pulse driving branch and the negative pulse driving branch. The clock driver further includes a pulse generator having positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.

US Patent:

20150365076, Dec 17, 2015

Filed:

Jun 13, 2014

Appl. No.:

14/303671

Inventors:

- Armonk NY, US
THOMAS J. BUCELOT - WAPPINGERS FALLS NY, US
ALAN J. DRAKE - ROUND ROCK TX, US
PHILLIP J. RESTLE - KATONAH NY, US
DAVID W. SHAN - AUSTIN TX, US
MRIGANK SHARAD - WEST LAFAYETTE IN, US

International Classification:

H03K 3/012
H03K 5/13
H03K 5/05

Abstract:

A clock driver and corresponding method are provided. The clock driver includes a multi-stage delay cell having logic circuitry and a plurality of serially connected delay elements. An input of the delay elements receives an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. An output of the delay elements connects to positive and negative pulse driving branches formed from the logic circuitry. The clock driver further includes a pulse generator forming positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.