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Simon M Bikulcius

age ~54

from San Jose, CA

Also known as:
  • Simon M Bikolcius
  • Simon Biklucius
Phone and address:
2034 Limewood Dr, San Jose, CA 95132
4082638044

Simon Bikulcius Phones & Addresses

  • 2034 Limewood Dr, San Jose, CA 95132 • 4082638044
  • Sunnyvale, CA
  • Milpitas, CA

Work

  • Company:
    Texas instruments
    Sep 2011
  • Address:
    Santa Clara
  • Position:
    Princ. circuit design

Education

  • Degree:
    BS
  • School / High School:
    San Jose State University
    1995 to 1998
  • Specialities:
    Electronics

Skills

Mixed Signal • Circuit Design • Semiconductors • Ic • Matlab • Analog • Bicmos • Debugging • Microcontrollers • System Architecture • Ic Layout • Cmos • Analog Circuit Design • Power Management • Automation • Electronics • Cadence Virtuoso • Pll • Integrated Circuit Design • Creative Thinking • Modeling • Ic Simulation • Spectre • Power Electronics • Low Power Design • Spice • Serdes • Cadence • Pcb Design • Verilog

Languages

English

Interests

Outdoors • Sports • Boating • Electronics

Industries

Electrical/Electronic Manufacturing

Us Patents

  • Semiconductor-Based Spiral Capacitor

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  • US Patent:
    6661079, Dec 9, 2003
  • Filed:
    Feb 20, 2002
  • Appl. No.:
    10/078844
  • Inventors:
    Simon Bikulcius - San Jose CA
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H01L 2900
  • US Classification:
    257532, 257531
  • Abstract:
    Increased capacitance per unit of area with reduced series resistance and inductance is provided by a semiconductor-based capacitor with a spiral shape. The capacitor utilizes a plurality of patterned metal layers that each have a first trace with a spiral shape and a second trace with a spiral shape. The second trace is formed between the loops of the first trace, and around the first trace.
  • Domain Power Notification System

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  • US Patent:
    6788511, Sep 7, 2004
  • Filed:
    Nov 9, 2001
  • Appl. No.:
    10/037735
  • Inventors:
    Simon Bikulcius - Sunnyvale CA
    Mark A. Landguth - La Jolla CA
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
  • International Classification:
    H02H 324
  • US Classification:
    361 92, 307 64
  • Abstract:
    A domain power notification system detects when a power domain experiences a power condition, such as lost power and low-voltage power, and communicates that information to the domains that communicate with the problem domain. As a result, the effected domains stop communicating with the problem domain without passing erroneous information.
  • System And Method For Domain Power Monitoring And Notification

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  • US Patent:
    7142404, Nov 28, 2006
  • Filed:
    Jun 9, 2004
  • Appl. No.:
    10/864137
  • Inventors:
    Simon Bikulcius - Sunnyvale CA, US
    Mark A. Landguth - La Jolla CA, US
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
  • International Classification:
    H02H 3/24
  • US Classification:
    361 92, 340663, 340635, 714 14
  • Abstract:
    A domain power notification system detects when a power domain experiences a power condition, such as lost power and low-voltage power, and communicates that information to the domains that communicate with the problem domain. As a result, the effected domains stop communicating with the problem domain without passing erroneous information.
  • Apparatus And Method For Testing High-Speed Serial Transmitters And Other Devices

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  • US Patent:
    8037371, Oct 11, 2011
  • Filed:
    May 14, 2007
  • Appl. No.:
    11/803231
  • Inventors:
    Simon Bikulcius - San Jose CA, US
    Vadim Tsinker - Belmont CA, US
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    G06K 5/04
    G11B 5/00
    G11B 20/20
  • US Classification:
    714700, 714724, 375224, 375226
  • Abstract:
    A testing device for testing a high-speed serial transmitter or other device includes an input stage having a first comparator, a second comparator, and a digital-to-analog converter. The first comparator compares first differential signals from a device under test. The second comparator compares the first differential signals and second differential signals from the digital-to-analog converter. An analysis unit identifies first beats based on an output of the first comparator and second beats based on an output of the second comparator. The analysis unit identifies one or more characteristics of the device under test (such as jitter, differential signal swing, and transition time) based on the first and second beats. A clock unit provides an adjustable clock signal to the comparators. The clock signal may have a frequency shift with respect to a frequency of the device under test.
  • Method And Apparatus For Generating A Power-On Reset With An Adjustable Falling Edge For Power Management

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  • US Patent:
    6515523, Feb 4, 2003
  • Filed:
    May 23, 2001
  • Appl. No.:
    09/864662
  • Inventors:
    Simon Bikulcius - Sunnyvale CA
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H03L 700
  • US Classification:
    327142, 327143, 327198
  • Abstract:
    A method and apparatus is directed to a power-on reset circuit for providing a power-on reset signal having a rising edge and an adjustable falling edge. A reference generator circuit produces two different reference signals in response to a power supply signal. The two reference signals are compared by a comparison circuit to produce a resulting reference signal. The resulting reference signal tracks the power supply signal until a first threshold potential is reached. When the first threshold potential is reached, a rising edge is produced in the power-on reset signal. The rising edge indicates that the power supply signal has reached an operating potential. A second threshold potential corresponds to the adjustable falling edge of the power-on reset signal. When the power supply signal decreases below the second threshold potential, the adjustable falling edge is produced in the power-on reset signal. The second threshold potential is adjusted when an adjustment circuit selectively couples additional transistors to the reference generator circuit.

Resumes

Simon Bikulcius Photo 1

Design Engineering Supervisor

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Location:
2034 Limewood Dr, San Jose, CA 95132
Industry:
Electrical/Electronic Manufacturing
Work:
Texas Instruments - Santa Clara since Sep 2011
Princ. Circuit Design

National Semiconductor since Jan 2008
Princ. Circuit Designer

National Semiconductor 2005 - 2007
Staff design
Education:
San Jose State University 1995 - 1998
BS, Electronics
De Anza College 1995
AA, General
San Jose State University 2000
ms, Electronics
Skills:
Mixed Signal
Circuit Design
Semiconductors
Ic
Matlab
Analog
Bicmos
Debugging
Microcontrollers
System Architecture
Ic Layout
Cmos
Analog Circuit Design
Power Management
Automation
Electronics
Cadence Virtuoso
Pll
Integrated Circuit Design
Creative Thinking
Modeling
Ic Simulation
Spectre
Power Electronics
Low Power Design
Spice
Serdes
Cadence
Pcb Design
Verilog
Interests:
Outdoors
Sports
Boating
Electronics
Languages:
English

Classmates

Simon Bikulcius Photo 2

San Jose State University...

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Graduates:
Simon Bikulcius (1995-1998),
Sam Pang (1996-1998),
Alex Yefimov (1992-1995)

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