Siegfried Hart

US Patent:

6621343, Sep 16, 2003

Filed:

Aug 7, 2001

Appl. No.:

09/924836

Inventors:

Siegfried Hart - Santa Cruz CA

Assignee:

Infineon Technologies AG

International Classification:

H03F 345

US Classification:

330254, 330133, 330134, 330258

Abstract:

A variable gain amplifier (âVGAâ) having an open loop architecture is disclosed. The VGA includes one or more gain cells coupled in the signal path to amplify a given input signal. The VGA further includes a replica gain cell having a gain servo circuit which amplifies a gain reference signal according to a programmable gain input and equalizes the amplified reference signal to the original unamplified reference signal, continuously generating a gain control input to the signal path gain cells based on the equalization. This gain control input reflects the gain set by the programmable gain input as adjusted for process, temperature and supply voltage variations. The replica gain cell further includes a common mode voltage servo circuit which senses the common mode voltage of the amplified reference signal and equalizes it to a common mode voltage reference, generating a common mode voltage control signal to the signal path gain cells to regulate their common mode voltage. This regulation of the common mode voltage of the signal path gain cells is compensated for process, temperature and supply voltage variations.

US Patent:

6661590, Dec 9, 2003

Filed:

May 25, 2001

Appl. No.:

09/865860

Inventors:

Sasan Cyrusian - Scotts Valley CA
Stephen J. Franck - Felton CA
Sriharsha Annadore - Santa Cruz CA
Elmar Bach - Santa Cruz CA
Siegfried Hart - Santa Cruz CA
Thomas Blon - Santa Cruz CA
William G. Bliss - Thornton CO
James Wilson Rae - Rochester MN
Michael Ruegg - Santa Cruz CA
Ulrich Huewels - Santa Cruz CA
Fritz Mistlberger - Sudmahrerweg 1, DE

Assignee:

Infineon Technologies AG - Munich

International Classification:

G11B 509

US Classification:

360 32, 360 51, 360 66

Abstract:

A method and apparatus for running an analog portion ( ) of a read/write channel ( ) from a highly regulated power supply ( ). The apparatus includes an analog portion ( ), a clock synthesizer ( ), and a highly regulated power supply ( ) connected to the analog portion ( ) and the clock synthesizer ( ). The analog portion ( ) and the clock synthesizer ( ) both comprise high voltage transistors which operate in a first voltage range and low voltage transistors which operate in a second voltage range, wherein the first voltage range is within the second voltage range. The highly regulated power supply ( ) supplies power that is within the first voltage range to the analog portion ( ) and the clock synthesizer ( ). The method includes generating power that is within the first voltage range using the highly regulated power supply ( ), and supplying the power to the analog portion ( ) and the clock synthesizer ( ).

US Patent:

6504397, Jan 7, 2003

Filed:

Sep 7, 2001

Appl. No.:

09/949260

Inventors:

Siegfried Hart - Santa Cruz CA
Palaksha Setty - Sunnyvale CA

Assignee:

Infineon Technologies North America Corp. - San Jose CA

International Classification:

H03K 1716

US Classification:

326 30, 326 27, 326 83, 327109

Abstract:

A differential line driver having integrated output termination resistors is disclosed. The termination resistors are a combination of a controlled transistor and a low precision resistor. The transistor calibrates-out the imprecision of the resistor based on a precise electrical reference. In a preferred embodiment the transistor is a CMOS transistor and the resistor is a CMOS resistor. The combination of a CMOS transistor and CMOS resistor features higher linearity and precision than a CMOS transistor alone due to the smaller effective drain-source voltage across the CMOS transistor. Moreover, the present invention discloses independent programmability of the integrated output termination resistor, the output common mode voltage, and the output amplitude. The value of the output termination resistor(s), the value of the output common mode voltage, and the value of the output amplitude are controlled independently and are continuously maintained with respect to a precise electrical reference. As a result, the value of the output termination resistance, the value of the output common mode voltage, and the value of the output amplitude are insensitive to manufacturing process tolerances and variations in temperature and supply voltage.