Shurong Zheng

US Patent:

55303862, Jun 25, 1996

Filed:

Nov 24, 1993

Appl. No.:

8/157712

Inventors:

James R. Kuo - Cupertino CA
Shurong Zheng - Sunnyvale CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03K 508
H03K 1760

US Classification:

327109

Abstract:

A storage charge reduction circuit for reducing the storage charge of a first bipolar transistor. The circuit includes a second field effect transistor connectable between the base of the first bipolar transistor and ground for conducting a compensation current from the base of the first bipolar transistor to ground. A third bipolar transistor is connected in series with a first resistor for conducting a first current from a first voltage supply through the first resistor to ground. Current mirror circuitry sets the gate-source voltage of the second field effect transistor so that the compensation current is proportional to the first current. The first current and the compensation current increase when temperature increases. In a preferred embodiment, the storage charge reduction circuit is used in a transmission line driver. The driver includes an output bipolar transistor connectable between the transmission line and ground for conducting current from the transmission line to ground.