Antoine Khoueir - Apple Valley MN, US Haiwen Xi - Prior Lake MN, US Shuiyuan Huang - Apple Valley MN, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
H01L 47/00
US Classification:
257 4
Abstract:
Programmable metallization memory cells that have an inert electrode and an active electrode positioned in a non-overlapping manner in relation to a substrate. A fast ion conductor material is in electrical contact with and extends from the inert electrode to the active electrode, the fast ion conductor including superionic clusters extending from the inert electrode to the active electrode. A metal layer extends from the inert electrode to the active electrode, yet is electrically insulated from each of the inert electrode and the active electrode by the fast ion conductor material. Methods for forming programmable metallization cells are also disclosed.
Yang Li - Bloomington MN, US Insik Jin - Eagan MN, US Harry Liu - Maple Grove MN, US Song S. Xue - Edina MN, US Shuiyuan Huang - Apple Valley MN, US Michael X. Tang - Bloomington MN, US
A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device.
Active Protection Device For Resistive Random Access Memory (Rram) Formation
Yongchul Ahn - Eagan MN, US Antoine Khoueir - Apple Valley MN, US Shuiyuan Huang - Apple Valley MN, US Peter Nicholas Manos - Eden Prairie MN, US Maroun Khoury - Burnsville MN, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
G11C 11/00
US Classification:
365148, 365171, 365226
Abstract:
Apparatus and method for providing overcurrent protection to a resistive random access memory (RRAM) cell during an RRAM formation process used to prepare the cell for normal read and write operations. In accordance with various embodiments, the RRAM cell is connected between a first control line and a second control line, and an active protection device (APD) is connected between the second control line and an electrical ground terminal. A formation current is applied through the RRAM cell, and an activation voltage is concurrently applied to the APD to maintain a maximum magnitude of the formation current below a predetermined threshold level.
Xuguang Wang - Maple Grove MN, US Shuiyuan Huang - Apple Valley MN, US Dimitar V. Dimitrov - Edina MN, US Michael Xuefei Tang - Bloomington MN, US Song S. Xue - Edina MN, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
H01L 29/92
US Classification:
257300, 257296, 257298, 257306, 257312, 257E29345
Abstract:
Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer is between the first insulating layer and second insulating layer. The solid electrolyte layer has a capacitance that is controllable between at least two states. A first electrode is electrically coupled to a first side of the solid electrolyte layer and is electrically coupled to a voltage source. A second electrode is electrically coupled to a second side of the solid electrolyte layer and is electrically coupled to the voltage source. Multi-bit memory units are also disclosed.
Programmable Metallization Memory Cells Via Selective Channel Forming
Haiwen Xi - Prior Lake MN, US Ming Sun - Eden Prairie MN, US Dexin Wang - Eden Prairie MN, US Shuiyuan Huang - Apple Valley MN, US Michael Tang - Bloomington MN, US Song S. Xue - Edina MN, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
H01L 29/66
US Classification:
257154, 257 9, 257E27004, 257E27071, 438 95
Abstract:
A programmable metallization memory cell that has an apertured insulating layer comprising at least one aperture therethrough positioned between the active electrode and the inert electrode. Superionic clusters are present within the at least one aperture, and may extend past the at least one aperture. Also, methods for making a programmable metallization memory cell are disclosed.
Programmable Metallization Memory Cells Via Selective Channel Forming
Haiwen Xi - Prior Lake MN, US Ming Sun - Eden Prairie MN, US Dexin Wang - Eden Prairie MN, US Shuiyuan Huang - Apple Valley MN, US Michael Tang - Bloomington MN, US Song S. Xue - Edina MN, US
Haiwen Xi - Prior Lake MN, US Ming Sun - Eden Prairie MN, US Dexin Wang - Eden Prairie MN, US Shuiyuan Huang - Apple Valley MN, US Michael Tang - Bloomington MN, US Song S. Xue - Edina MN, US
Assignee:
Seagate Technology LLC - Scotts Valley CA
International Classification:
H01L 29/66
US Classification:
257154, 257 9, 257E27004, 257E27071, 438 95
Abstract:
Methods for making a programmable metallization memory cell are disclosed.
Yang Li - Bloomington MN, US Insik Jin - Eagan MN, US Harry Liu - Maple Grove MN, US Song S. Xue - Edina MN, US Shuiyuan Huang - Apple Valley MN, US Michael X. Tang - Bloomington MN, US
A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device.
D-Wave Systems Inc.
Technical Lead of Qpu Microfabrication
Polar Semiconductor, Llc Oct 2009 - Apr 2017
Process Engineering Section Manager
Western Digital Jul 2009 - Oct 2009
Staff Enginner - Process Development
Seagate Technology Mar 2007 - Jul 2009
Senior Staff Integration Engineer R and D
Cypress Semiconductor Corporation May 2001 - Feb 2007
Senior and Staff and Senior Staff Process Development Engineer R and D
Education:
Tsinghua University 1992 - 1997
Doctorates, Doctor of Philosophy, Chemical Engineering
Tsinghua University 1990 - 1992
Bachelors, Bachelor of Arts, Management
Tsinghua University 1987 - 1992
Bachelor of Engineering, Bachelors, Chemical Engineering
Skills:
Design of Experiments Semiconductors Cmos R&D Cvd Etching Thin Films Spc Sensors Metrology Jmp Process Integration Characterization Failure Analysis Process Simulation Diffusion Process Engineering Yield Ic Nanotechnology Pvd Pecvd Semiconductor Industry Silicon Engineering Management Mixed Signal Photolithography Doe Electronics Manufacturing Clean Materials Science Six Sigma Simulations
Languages:
Mandarin English
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