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Shri Sagar Dwivedi

age ~49

from San Jose, CA

Also known as:
  • Shri S Dwivedi
  • Shrisagar Sagar Dwivedi
  • Shrisagar S Dwivedi
  • Sagar Dwivedi
  • R D
Phone and address:
685 Crestmoor Dr, San Jose, CA 95129

Shri Dwivedi Phones & Addresses

  • 685 Crestmoor Dr, San Jose, CA 95129
  • Sunnyvale, CA
  • Merced, CA
  • Santa Clara, CA

Us Patents

  • Column Multiplexer Circuitry

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  • US Patent:
    20210304816, Sep 30, 2021
  • Filed:
    Aug 11, 2020
  • Appl. No.:
    16/990951
  • Inventors:
    - Cambridge, GB
    Fakhruddin Ali Bohra - San Jose CA, US
    Shri Sagar Dwivedi - San Jose CA, US
    Vidit Babbar - Bangalore, IN
  • International Classification:
    G11C 11/418
    G11C 11/419
  • Abstract:
    Various implementations described herein are related to a device having memory architecture having multiple bitcell arrays. The device may include column multiplexer circuitry coupled to the memory architecture via multiple bitlines for read access operations. The column multiplexer circuitry may perform read access operations in the multiple bitcell arrays via the bitlines based on a sense amplifier enable signal and a read multiplexer signal. The device may include control circuitry that provides the read multiplexer signal to the column multiplexer circuitry based on a clock signal and the sense amplifier enable signal so that the column multiplexer circuitry is able to perform the read access operations.
  • Dummy Wordline Design Techniques

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  • US Patent:
    20210065839, Mar 4, 2021
  • Filed:
    Aug 29, 2019
  • Appl. No.:
    16/555964
  • Inventors:
    - Cambridge, GB
    Shri Sagar Dwivedi - San Jose CA, US
    Fakhruddin Ali Bohra - San Jose CA, US
    Gaurav Rattan Singla - San Jose CA, US
  • International Classification:
    G11C 29/00
    G11C 11/4091
    G11C 11/16
    G11C 8/18
  • Abstract:
    Various implementations described herein are directed to a device having memory with an array of bitcells arranged in columns and rows, wherein a first number of columns represents a first number of output bits, and a second number of columns represents a second number of output bits. The device may include dummy wordline (DWL) circuitry having multiple DWL paths including a first DWL path disposed along the first number of columns and a second DWL path disposed along the second number of columns. The first DWL path has a shorter length than the second DWL path so as to allow for faster operation of the bitcells in the memory associated with the first number of output bits.
  • Bitline Precharge Circuitry

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  • US Patent:
    20200388309, Dec 10, 2020
  • Filed:
    Jun 7, 2019
  • Appl. No.:
    16/435425
  • Inventors:
    - Cambridge, GB
    Gaurav Rattan Singla - San Jose CA, US
    Fakhruddin Ali Bohra - San Jose CA, US
    Shri Sagar Dwivedi - San Jose CA, US
  • International Classification:
    G11C 7/12
    G11C 7/22
  • Abstract:
    Various implementations described herein are directed to a device having an array of bitcells with bitlines coupled to columns of the bitcells. The device may include one or more switch structures that are coupled between the bitlines and a supply voltage, and the switch structures may be configured to precharge the bitlines to the supply voltage when activated. In some instances, the supply voltage may refer to ground or a ground related voltage having a voltage near or equal to zero volts (0V).
  • Coupling Compensation Circuitry

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  • US Patent:
    20200219559, Jul 9, 2020
  • Filed:
    Mar 16, 2020
  • Appl. No.:
    16/820487
  • Inventors:
    - Cambridge, GB
    Lalit Gupta - Cupertino CA, US
    Fakhruddin Ali Bohra - San Jose CA, US
    Shri Sagar Dwivedi - San Jose CA, US
  • International Classification:
    G11C 11/419
  • Abstract:
    Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.
  • High-Speed Memory Architecture

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  • US Patent:
    20200005836, Jan 2, 2020
  • Filed:
    Jun 29, 2018
  • Appl. No.:
    16/024449
  • Inventors:
    - Cambridge, GB
    Fakhruddin Ali Bohra - San Jose CA, US
    Jitendra Dasani - Cupertino CA, US
    Shri Sagar Dwivedi - San Jose CA, US
    Vivek Nautiyal - Milpitas CA, US
    Gaurav Rattan Singla - San Jose CA, US
  • International Classification:
    G11C 7/12
    G11C 7/18
    G11C 7/22
    G11C 8/14
  • Abstract:
    Various implementations described herein refer to an integrated circuit having memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays. The first pair of bank arrays may have a first number of rows, and the second pair of bank arrays have a second number of rows that is different than the first number of rows. The integrated circuit may include bank multiplexer circuitry that is coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel. The bank multiplexer circuitry may provide an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal.
  • Coupling Compensation Circuitry

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  • US Patent:
    20190325948, Oct 24, 2019
  • Filed:
    Apr 23, 2018
  • Appl. No.:
    15/960475
  • Inventors:
    - Cambridge, GB
    Lalit Gupta - Cupertino CA, US
    Fakhruddin Ali Bohra - San Jose CA, US
    Shri Sagar Dwivedi - San Jose CA, US
  • International Classification:
    G11C 11/419
  • Abstract:
    Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.
  • Integrated Circuit Using Discharging Circuitries For Bit Lines

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  • US Patent:
    20190325949, Oct 24, 2019
  • Filed:
    Apr 23, 2018
  • Appl. No.:
    15/960482
  • Inventors:
    - Cambridge, GB
    Jitendra Dasani - Cupertino CA, US
    Vivek Nautiyal - Milpitas CA, US
    Shri Sagar Dwivedi - San Jose CA, US
    Fakhruddin Ali Bohra - San Jose CA, US
  • International Classification:
    G11C 11/419
    G11C 11/412
  • Abstract:
    Various implementations described herein may refer to an integrated circuit using discharging circuitries for bit lines. In one implementation, an integrated circuit may include a memory array having memory cells, where the memory cells are arranged into columns and configured to be accessed using bit line pairs. The integrated circuit may also include discharging circuitries to selectively discharge the bit line pairs, where a respective discharging circuitry is coupled to a negative supply voltage node of a respective column of memory cells. The respective discharging circuitry may discharge a bit line pair of the respective column to a first voltage when the bit line pair is selected for a memory operation, and may discharge the bit line pair of the respective column to a second voltage when the bit line pair is not selected for a memory operation, where the second voltage is greater than the first voltage.
  • Transition Coupling Circuitry For Memory Applications

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  • US Patent:
    20190244656, Aug 8, 2019
  • Filed:
    Feb 7, 2018
  • Appl. No.:
    15/891212
  • Inventors:
    - Cambridge, GB
    Andy Wangkun Chen - Austin TX, US
    Sharryl Renee Dettmer - Austin TX, US
    Lalit Gupta - Cupertino CA, US
    Jitendra Dasani - Cupertino CA, US
    Yeon Jun Park - San Jose CA, US
    Shri Sagar Dwivedi - San Jose CA, US
    Fakhruddin Ali Bohra - San Jose CA, US
  • International Classification:
    G11C 11/4097
    G11C 7/18
    G11C 11/419
    H01L 27/11
  • Abstract:
    Various implementations described herein refer to an integrated circuit having memory circuitry. The memory circuitry may include a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair. The integrated circuit may include first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry. The integrated circuit may include second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs. The first bitline pair and the second bitline pair may be on a lower metal layer, and the jumper bitline pairs may be on a higher metal layer.

Youtube

SHREE TECH COMPUTER EDUCATION my dreams come ...

shree tech computer education

  • Category:
    Education
  • Uploaded:
    03 Apr, 2009
  • Duration:
    5m 30s

SHRI SUNDARKAND PATH SEVA SAMITI, SIROHI ( RA...

Dev nagari Sirohi me Sundarkand ka path har Shanivar or Mangalvar ko N...

  • Category:
    People & Blogs
  • Uploaded:
    20 Jul, 2010
  • Duration:
    3m 36s

Mera Juta Hai Japani by Rajnikant superb danc...

Ek Shaam Attachowk Ke Naam a cultural programme was presented by the u...

  • Category:
    News & Politics
  • Uploaded:
    15 Feb, 2010
  • Duration:
    5m 52s

Musical yoga asnas by child yoga Guru Tejaswi...

Ek Shaam Attachowk Ke Naam a cultural programme was presented by the u...

  • Category:
    News & Politics
  • Uploaded:
    13 May, 2010
  • Duration:
    7m 12s

Flag Hoisting ceremony by Shri Shivakant Dwiv...

Flag Hoisting ceremony by Shri Shivakant Dwivedi, Addl District Magist...

  • Category:
    News & Politics
  • Uploaded:
    15 Aug, 2010
  • Duration:
    1m 20s

Greater Noida Social workers Suneel Dwivedi a...

Social workers of Delta 1, Suneel Dwivedi and DP Gautam attacked by an...

  • Category:
    News & Politics
  • Uploaded:
    03 Jul, 2010
  • Duration:
    1m 9s

Must Radio Team RJ Ashish Bhatia,RJ and Produ...

must radio team rj ashish bhatia rj and producer amit dwivedi and shri...

  • Category:
    Nonprofits & Activism
  • Uploaded:
    15 Feb, 2010
  • Duration:
    37s

Ramleela Addl District Magistrate Shri Shivak...

Ramleela Addl District Magistrate Shri Shivakant Dwivedi address

  • Category:
    News & Politics
  • Uploaded:
    11 Oct, 2010
  • Duration:
    2m 10s

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Shri Dwivedi

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Shri Prakash Dwivedi

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Shri Dwivedi Photo 4

Shri Prakash Dwivedi

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Shri Dwivedi Photo 5

Shri Hari Dwivedi

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Shri Ram Dwivedi

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Shri Dwivedi

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