Sheila Faye Chopin

US Patent:

7015585, Mar 21, 2006

Filed:

Dec 18, 2002

Appl. No.:

10/323296

Inventors:

Susan H. Downey - Austin TX, US
Sheila F. Chopin - Austin TX, US
Peter R. Harper - Round Rock TX, US
Sohrab Safai - Round Rock TX, US
Tu-Anh Tran - Austin TX, US
Alan H. Woosley - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23/48

US Classification:

257774, 257773, 257776, 257662, 257663, 257690, 257678, 257786

Abstract:

An integrated circuit is packaged using a package substrate that has a bottom side with a regular array of connection points and a top side with the integrated circuit on it. The package substrate also has vias that are present to provide electrical connection between the top and bottom sides. The vias have a via capture pad that is used to directly receive a wire bond. Thus, the wires from the integrated circuit to the top side directly contact the vias at their capture pads. In such a connection there is then no need for a trace from location where the wire is bonded on the top side to the via. This saves cost. Further this makes the package substrate useful for more than one type of integrated circuit.

US Patent:

7172927, Feb 6, 2007

Filed:

Dec 18, 2003

Appl. No.:

10/740303

Inventors:

Yuan Yuan - Austin TX, US
Sheila F. Chopin - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/44
H01L 21/48
H01L 21/50

US Classification:

438127, 257E21502

Abstract:

During the curing process of the package strips, especially during post encapsulant cure (PEC), undesirable warpage of package strips occurs. A carrier having angled lands and side-insertion clamp structures with angled clamp fins may be used to control this cure-induced warpage of package strips during PEC. In one embodiment, the angled lands and angled side-insertions clamps are used to clamp the edges of the package strip in order to introduce an intentional deformation which counters warpage which occurs during PEC. The angled lands and side-insertion clamps may be at any angle (fixed or adjustable). The side-insertion clamps may be inserted before or after insertion of the package strips into the carrier. Once the package strips are in the carrier and resting on the angled lands, a force may be applied to the side-insertion clamps to clamp the edges of the package strips between a clamp fin and an angled land.

US Patent:

7215014, May 8, 2007

Filed:

Jul 29, 2004

Appl. No.:

10/901844

Inventors:

Peng Su - Austin TX, US
Sheila F. Chopin - Austin TX, US
Nhat D. Vo - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 23/495

US Classification:

257677

Abstract:

A packaged integrated circuit includes a die surrounded by an encapsulant in which leads are used to electrically connect the die, which is internal to the encapsulant, externally. The leads have a primary metal that is used for electrical conduction and physical support. The external portion of the lead is coated with another metal, typically tin, that is useful for soldering. This tin layer is formed in a manner that ensures that it is porous. Although porous is generally thought to be a bad characteristic, it turns out to be very effective in absorbing stress and thus retarding whisker growth. Whisker growth, which can short adjacent leads together as well as cause other deleterious effects, has been a major source of failures in packaged integrated circuits. An additional layer of very thin tin that is non-porous can be added before or after the porous tin layer has been deposited.

US Patent:

7803662, Sep 28, 2010

Filed:

Sep 24, 2007

Appl. No.:

11/860125

Inventors:

Yuan Yuan - Austin TX, US
Sheila F. Chopin - Round Rock TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/00

US Classification:

438112, 438106, 438127

Abstract:

A method for curing an encapsulant that surrounds a plurality of integrated circuits on a strip that forms a strip assembly is provided. The strip assembly is composed of units for packaging and the units each have edges defining a perimeter of the unit. The strip assembly is placed on a shelf. Pressure from deformable material or springs is applied to the strip assembly in regions of the strip. The regions are located at one of a group of locations consisting of along unit edges and centered between unit edges. Heat of sufficient temperature is applied for a sufficient duration to cure the encapsulant. The step of applying pressure continues during the application of heat for curing.

US Patent:

20050122198, Jun 9, 2005

Filed:

Dec 5, 2003

Appl. No.:

10/729531

Inventors:

Yaping Zhou - Austin TX, US
Susan Downey - Austin TX, US
Sheila Chopin - Austin TX, US
Tu-Anh Tran - Austin TX, US
Alan Woosley - Austin TX, US
Peter Harper - Lucas TX, US
Perry Pelley - Austin TX, US

International Classification:

H01F005/00

US Classification:

336200000

Abstract:

An inductive device () is formed above a substrate () having a conductive coil formed around a core (). The coil comprises segments formed from a first plurality of bond wires () and a second plurality of bond wires (). The first plurality of bond wires () extends between the core () and the substrate (). Each of the first plurality of bond wires is coupled to two of a plurality of wire bond pads (). The second plurality of bond wires () extends over the core () and is coupled between two of the plurality of wire bond pads (). A shield () includes a portion that is positioned between the core () and the substrate ().

US Patent:

20070031996, Feb 8, 2007

Filed:

Apr 16, 2004

Appl. No.:

10/553529

Inventors:

Sheila Chopin - Austin TX, US
Peter Harper - Lucas TX, US
Jose Montes De Oca - New Braunfels TX, US
Kim Tan - Satu, MY
Lan Han - Klang, MY

International Classification:

H01L 21/00

US Classification:

438122000, 438121000, 438123000, 438124000, 438113000

Abstract:

An integrated circuit is packaged, in one embodiment, by wire bonding to pads supported by tape. The tape also supports traces that run from the wire bonded location to a pad for solder balls. A heat spreader is thermally connected to the integrated circuit and is located not just in the area under the die but also extends to the edge of the package in the area outside the wire bonding location. This outer area is thermally connected to the area under the die by thermal bars that run between some of the wire bond locations. During the manufacturing of the package the heat spreader is connected to slotted rails by tie bars. During singulation, the tie bars are easily broken or sawed because they are significantly reduced in thickness from the thickness of the heat spreader as a whole.

US Patent:

20120193737, Aug 2, 2012

Filed:

Dec 21, 2011

Appl. No.:

13/333996

Inventors:

Xingshou Pang - Tianjin, CN
Sheila F. Chopin - Round Rock TX, US
Jun Li - Tianjin, CN
Xuesong Xu - Tianjin, CN

Assignee:

FREESCALE SEMICONDUCTOR, INC - Austin TX

International Classification:

H01L 29/82
H01L 43/12

US Classification:

257421, 438 3, 438107, 257659, 257E43006, 257E29323

Abstract:

A method of packaging a magnetoresistive random access memory (MRAM) die includes providing a lead frame having a die pad and lead fingers. The MRAM die is attached to the die pad with a first die attach adhesive and bond pads of the MRAM die are electrically connected to the lead fingers of the lead frame with wires using a wire bonding process. A pre-formed composite magnetic shield is attached to a top surface of the MRAM die with a second die attach adhesive. The magnetic shield includes a magnetic permeable filler material dispersed within an organic matrix. An encapsulating material is dispensed onto a top surface of the lead frame, MRAM die and magnetic shield such that the encapsulating material covers the MRAM die and the magnetic shield. The encapsulating material is then cured.

US Patent:

20130319129, Dec 5, 2013

Filed:

May 31, 2012

Appl. No.:

13/484353

Inventors:

Varughese Mathew - Austin TX, US
Sheila F. Chopin - Round Rock TX, US

Assignee:

FREESCALE SEMICONDUCTOR, INC. - Austin TX

International Classification:

G01N 3/08
H01L 21/66
H01L 21/56

US Classification:

73827, 438 15, 438 14, 257E21502, 257E21521

Abstract:

A technique for testing the compatibility of an encapsulation material and a wire bond included at an unencapsulated assembly. The technique includes immersing the assembly in an encapsulating compound extract. The assembly includes a semiconductor die and a bonding wire affixed to a metalized pad of the semiconductor die by the wire bond. After the immersing, a mechanical strength of the wire bond is determined.