Rownak J Zaman

US Patent:

20080280414, Nov 13, 2008

Filed:

May 7, 2007

Appl. No.:

11/745214

Inventors:

Rownak Jyoti Zaman - Austin TX, US

International Classification:

H01L 21/331

US Classification:

438378, 257E2137

Abstract:

Systems and methods for fabricating bipolar and/or biCMOS devices are described. A combination of bipolar fabrication steps and CMOS, and in particular, SOI fabrication steps may be used. In one embodiment, a collector region and/or a base region of a bipolar device may be formed using a bipolar mask, and an emitter region may be defined by a CMOS mask.

US Patent:

20070117311, May 24, 2007

Filed:

Nov 23, 2005

Appl. No.:

11/286704

Inventors:

Rownak Zaman - Austin TX, US

International Classification:

H01L 21/8242
H01L 29/76

US Classification:

438253000, 257314000

Abstract:

Single-transistor memory cell including a three-dimensional capacitor and methods for fabricating the cell are disclosed. The method includes steps for defining a source and drain, forming a channel between the source and drain, and forming a gate area of a transistor. The method also includes forming a first and second capacitor plate of a three-dimensional capacitor coupled to the drain of the transistor. In one respect, the first capacitor plate may be formed substantially simultaneously with the step of forming the channel. Additionally, the second capacitor plate may be formed substantially simultaneously with the step of defining the gate area of the transistor. The capacitor may include a three-dimensional fin capacitor and the transistor may include, for example, a multi-gate field effect transistor, a fin field effect transistor, a tri-gate transistor, a Π transistor, and a Ω transistor.