Ronald G Filippi

US Patent:

6383920, May 7, 2002

Filed:

Jan 10, 2001

Appl. No.:

09/757894

Inventors:

Ping-Chuan Wang - New Paltz NY
Ronald G. Filippi - Wappingers Falls NY
Robert D. Edwards - Malboro NY
Edward W. Kiewra - Verbank NY
Roy C. Iggulden - Newburgh NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 214763

US Classification:

438639, 438637, 438638, 438672

Abstract:

The present invention relates generally to a method of enclosing a via in a dual damascene process. In one embodiment of the disclosed method, the via is etched first and a first barrier metal or liner is deposited in the via, the trench is then etched and a second barrier metal or liner is deposited in the trench, and finally the via and trench are filled or metallized in a dual damascene process, thereby forming a via or interconnect and a line. Alternatively, the trench may be etched first and a first barrier metal or liner deposited in the trench, then the via is etched and a second barrier metal or liner is deposited in the via, and finally the trench and via are filled or metallized in a dual damascene process. The barrier metal or liner encloses the via, thereby reducing void formation due to electromigration.

US Patent:

6417572, Jul 9, 2002

Filed:

Jul 16, 1999

Appl. No.:

09/354592

Inventors:

Dureseti Chidambarrao - Weston CT
Ronald G. Filippi - Wappingers Falls NY
Robert Rosenberg - Cortlandt Manor NY
Thomas M. Shaw - Peekskill NY
Timothy D. Sullivan - Underhill VT
Richard A. Wachnik - Mount Kisco NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348

US Classification:

257773, 257775, 257765

Abstract:

A process for producing a multi-level semiconductor device having metal interconnections with insulating passivation layers and the product produced thereby. The product and process improve the resistance of the metallization interconnections to extrusion-short electromigration failures by preventing the insulating passivation layers from cracking. The product and process also reduce the level of resistance saturation or the maximum resistance shift caused by electromigration. By replacing wide-line metallization interconnection conducting lines surrounded by insulating passivation layers with two or more narrow, parallel conducting lines having aspect ratios less than or equal to unity with passivation layers located in between, the incidence of passivation cracking and extrusion-short failures is reduced. The process is especially suited for use in multi-level wiring structures in which the wiring levels have diffusion barriers between the wiring levels caused by redundant metallization layers, interlevel connections, or both.

US Patent:

6518670, Feb 11, 2003

Filed:

Mar 6, 2002

Appl. No.:

10/091643

Inventors:

Jack A. Mandelman - Stormville NY
Ronald G. Filippi - Wappingers Falls NY
Jeffrey P. Gambino - Westford VT
Richard A. Wachnik - Mt. Kisco NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2940

US Classification:

257752, 257774, 257750, 257763, 257764, 257758

Abstract:

A semiconductor device includes interconnected conductor lines comprising a lower Interlayer Dielectric (ILD) layer having a top surface formed on a substrate. Several lower conductor lines are formed on the top surface of the lower ILD layer surrounded by an insulator formed on the lower ILD layer. Each of a set of resistive studs has sidewalls, a lower end and an upper end and it is joined to the top of the lower conductor line at the lower end. There are several intermediate conductor lines formed between the resistive studs separated from adjacent studs by a liner layer and a capacitor dielectric layer. Upper conductor lines are formed on a upper level. Each has a bottom surface in contact with a corresponding one of the resistive studs. A central ILD layer is formed below the intermediate conductor to electrically insulate and separate the intermediate conductor lines from the lower conductor lines. A upper ILD layer overlies the intermediate conductor for electrically insulating and separating the intermediate conductor lines from the upper conductor lines.

US Patent:

6803662, Oct 12, 2004

Filed:

Dec 21, 2001

Appl. No.:

10/026117

Inventors:

Ping-Chuan Wang - New Paltz NY
Kevin H. Brelsford - Hyde Park NY
Ronald Filippi - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348

US Classification:

257774, 257734, 257750, 257758, 257759

Abstract:

A reinforced semiconductor interconnect structure, having the following components: (1) A first metal interconnect disposed in a first material, the first metal interconnect having a line portion and at least one via portion, an anode section and a cathode section, the via portion of the first metal interconnect located in the anode section, the line portion of the first metal interconnect having a top, bottom and terminus side, wherein at least a part of the bottom side of the line portion of the first metal interconnect in contact with the first dielectric; and (2) a first reinforcement disposed in the first material, the first reinforcement in contact with at least the bottom side of the first metal interconnect, the first reinforcement comprising a second material, the second material being electrically nonconductive; and wherein the second material has a greater mechanical rigidity than the first material.

US Patent:

6870263, Mar 22, 2005

Filed:

Mar 31, 1998

Appl. No.:

09/052688

Inventors:

Lawrence A. Clevenger - Lagrangeville NY, US
Ronald G. Filippi - Wappingers Falls NY, US
Mark Hoinkis - Fishkill NY, US
Jeffery L. Hurd - Marlboro NY, US
Roy C. Iggulden - Newburgh NY, US
Herbert Palm - Hoehenkirchen-Siegertsbrunn, DE
Hans W. Poetzlberger - Munich, DE
Kenneth P. Rodbell - Poughquag NY, US
Florian Schnabel - Wappingers Falls NY, US
Stefan Weber - Fishkill NY, US
Ebrahim A. Mehter - Wappingers Falls NY, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

H01L023/48

US Classification:

257750, 257767

Abstract:

A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.

US Patent:

6989282, Jan 24, 2006

Filed:

Apr 1, 2004

Appl. No.:

10/815418

Inventors:

Ronald Gene Filippi - Wappingers Falls NY, US
Lynne Marie Gignac - Beacon NY, US
Vincent J. McGahay - Poughkeepsie NY, US
Conal Eugene Murray - Yorktown Heights NY, US
Hazara Singh Rathore - Stormville NY, US
Thomas M. Shaw - Peekskill NY, US
Ping-Chuan Wang - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/66

US Classification:

438 14, 438637, 438638, 438672, 438673, 438700

Abstract:

A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.

US Patent:

7098054, Aug 29, 2006

Filed:

Feb 20, 2004

Appl. No.:

10/783462

Inventors:

Ronald Gene Filippi - Wappingers Falls NY, US
Jason Paul Gill - Essex VT, US
Vincent J. McGahay - Poughkeepsie NY, US
Paul Stephen McLaughlin - Poughkeepsie NY, US
Conal Eugene Murray - Yorktown Heights NY, US
Hazara Singh Rathore - Stormville NY, US
Thomas M. Shaw - Peekskill NY, US
Ping-Chuan Wang - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/66

US Classification:

438 18, 438638, 438927, 257 48, 29593, 324765

Abstract:

A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

US Patent:

7119545, Oct 10, 2006

Filed:

Sep 29, 2004

Appl. No.:

10/711641

Inventors:

Ishtiaq Ahsan - Wappingers Falls NY, US
Ronald Gene Filippi - Wappingers Falls NY, US
Roy Charles Iggulden - Newburgh NY, US
Edward William Kiewra - Verbank NY, US
Ping-Chuan Wang - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/08
G01R 27/26

US Classification:

324519, 324663, 324686

Abstract:

A method and apparatus for detecting metal extrusion associated with electromigration (EM) under high current density situations within an EM test line by measuring changes in capacitance associated with metal extrusion that occurs in the vicinity of the charge carrying surfaces of one or more capacitors situated in locations of close physical proximity to anticipated sites of metal extrusion on an EM test line are provided. The capacitance of each of the one or more capacitors is measured prior to and then during or after operation of the EM test line so as to detect capacitance changes indicating metal extrusion.