Robert P Boland

Author:

Robert Boland

ISBN #:

0810833239

US Patent:

7017140, Mar 21, 2006

Filed:

Nov 25, 2002

Appl. No.:

10/303441

Inventors:

Christopher L. Hayes - Hudson NH, US
Peter Simonson - Greenville NH, US
Frank Stroili - Hollis NH, US
Matthew Thiele - Hampstead NH, US
Robert P. Boland - Wilmington MA, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH

International Classification:

G06F 17/50

US Classification:

716 17, 716 16, 716 18

Abstract:

A multi-level framework that allows an application to be developed independent of the chip or board, and any dependency is built in as part of the framework of the field programmable device (FPD). A shell configuration called a ‘wrapper’ has a standard look, feel and form factor that provides the interface between the high density language (HDL) application and a standardized and board independent HDL shell, thus isolating the HDL core. A second wrapper is a board specific HDL shell that interacts with the standardized shell. Any application that has the same look, feel and form factor has a common interface that allows various system boards to communicate, providing a mechanism for creating a HDL application component independent of the hardware. An outer shell binds the system to some board and talks to the application program interface (API) layer and the code layer to the outside world, such as the operating system.

US Patent:

7559056, Jul 7, 2009

Filed:

Feb 23, 2005

Appl. No.:

11/063951

Inventors:

Robert P. Boland - Wilmington MA, US
Peter Simonson - Greenville NH, US
Jeffrey F. Bryant - Londonderry NH, US
Douglas K. Dalrymple - Nashua NH, US
David R. Wardwell - Bedford NH, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH

International Classification:

G06F 9/45

US Classification:

717149

Abstract:

A reconfigurable distributed signal processing system uses an object-oriented component-framework architecture in which the system permits large-scale software reuse. This is accomplished by the use of a framework and a number of reusable, reconfigurable software components that are hardware independent.

US Patent:

7573863, Aug 11, 2009

Filed:

Aug 22, 2002

Appl. No.:

10/225701

Inventors:

Robert P. Boland - Wilmington MA, US
Peter Simonson - Greenville NH, US
Peter O. Luthi - Nashua NH, US
Matthew J. Thiele - Hampstead NH, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH

International Classification:

H04J 3/06

US Classification:

370350, 370509

Abstract:

In a communications or jamming system, accurate timing for the control of the frequency, amplitude, modulation type, pulse repetition rate or other transmit characteristics is achieved for the transmission of digitally processed packetized signals through the use of standard non-realtime off-the-shelf components for the digital processing and a realtime interface which reads transmit chain headers and, with the assistance of a precise time reference, assures that the transmit chain is configured in time to transmit the packets. Note that the realtime interface assures nanosecond timing accuracy regardless of timing errors introduced by the off-the-shelf components used in upstream digital processing.

US Patent:

7573864, Aug 11, 2009

Filed:

Aug 22, 2002

Appl. No.:

10/225707

Inventors:

Robert P. Boland - Wilmington MA, US
Peter Simonson - Greenville NH, US
Peter O. Luthi - Nashua NH, US
Matthew J. Thiele - Hampstead NH, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH

International Classification:

H04J 3/06

US Classification:

370350, 370509

Abstract:

In a communications or jamming system, accurate timing of the transmission of digitally processed signals is accomplished through the use of standard off-the-shelf components. In order to eliminate the need for high-cost, difficult to develop, specific digital hardware or realtime synchronous software not available from the standard off-the-shelf components, the output from the non-real time components is coupled to a realtime interface that assures nanosecond timing accuracy regardless of timing errors introduced by the off-the-shelf components. In one embodiment, the signals to be transmitted are digitized and then packetized, with the data to be transmitted reconstructed using non-real time digital processing. In order to establish the exact time for transmission, the packet is given a time stamp in the form of a header which indicates the exact time at which the packet is to be transmitted by the communications system, with the packet with header being transmitted to a storage buffer, the output of which is coupled to a realtime interface including a precise time output gate, the timing of which is controlled by a precision time reference having nano-second accuracy.

US Patent:

7580404, Aug 25, 2009

Filed:

Jun 26, 2003

Appl. No.:

10/530160

Inventors:

Matthew J. Thiele - Hampstead NH, US
Robert P. Boland - Wilmington MA, US
Peter O. Luthi - Nashua NH, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH

International Classification:

H04L 12/50
G06F 17/00

US Classification:

370380, 709221

Abstract:

A reconfigurable compute engine interconnect fabric includes a reconfigurable interconnect layer ( FIG. ) between an application layer () and a physical layer () which identifies the input and output pins for the engine and their functions.

US Patent:

8095927, Jan 10, 2012

Filed:

Apr 14, 2009

Appl. No.:

12/386136

Inventors:

Robert P. Boland - Wilmington MA, US
Peter Simonson - Greenville NH, US
Jeffrey F. Bryant - Londonderry NH, US
Douglas K. Dalrymple - Nashua NH, US
David R Wardwell - Bedford NH, US

Assignee:

Wisterium Development LLC - Wilmington DE

International Classification:

G06F 9/445

US Classification:

717178

Abstract:

A signal intelligence system comprising a plurality of software components that are programmable to provide a signal intelligence function. The signal intelligence system includes a processor system having a plurality of interconnected processor devices and a plurality of processor managers that are connected to the processor devices and are configured to control software components associated with the processor devices. Further, the signal intelligence system has a framework manager that is configured to interact with the plurality of processor managers to control the processor devices and effectuate the signal intelligence function.

US Patent:

8411676, Apr 2, 2013

Filed:

Aug 24, 2009

Appl. No.:

12/546657

Inventors:

Matthew J. Thiele - Hampstead NH, US
Robert P. Boland - Wilmington MA, US
Peter O. Luthi - Nashua NH, US

Assignee:

Wisterium Development LLC - Wilmington DE

International Classification:

H04L 12/50

US Classification:

370360, 370380, 370469, 709221

Abstract:

A reconfigurable compute engine interconnect fabric includes a reconfigurable interconnect layer (, FIG. ) between an application layer () and a physical layer () which identifies the input and output pins for the engine and their functions.

US Patent:

20040045007, Mar 4, 2004

Filed:

Aug 30, 2002

Appl. No.:

10/233338

Inventors:

Robert Boland - Wilmington MA, US
Peter Simonson - Greenville NH, US
Jeffrey Bryant - Londonderry NH, US
Douglas Dalrymple - Nashua NH, US
David Wardwell - Bedford NH, US

Assignee:

BAE SYSTEMS INFORMATION ELECTRONIC SYSTEMS INTEGRATION, INC.

International Classification:

G06F009/00

US Classification:

719/315000

Abstract:

A reconfigurable distributed signal processing system uses an object-oriented component-framework architecture in which the system permits large-scale software reuse. This is accomplished by the use of a framework and a number of reusable, reconfigurable software components that are hardware independent. The components communicate over a data fabric using open published APIs over one or more data communications mechanisms. Interchangeable software components are used that perform the signal processing. Interchangeability is assured by each component meeting a required interface in which the component inherits the required interface elements from component base classes. This use of inheritance to assure interface compliance also reduces the programming work required for developing a component. Most importantly, the interchangeable components are reconfigurable into various systems at runtime, as defined by a Plan. A Plan is a schematic of the configuration of the various components to be used to solve a particular signal processing problem which includes the list of components, what computer each component is to execute on, how the components are interconnected, and the initial parameter values of the components. The system functionality and capability can be reconfigured at runtime based on a Plan read by a software element of the framework, the Framework Manager. Moreover, the source code for the components is platform independent. The system is able to use heterogeneous commercial off-the-shelf hardware to minimize equipment costs and lower non-recurring engineering costs as well. The system uses the object-oriented programming and software development to reduce time to market and to ensure program success while at the same time exploiting a standard development methodology.