Rashmi Jha

US Patent:

7754594, Jul 13, 2010

Filed:

Jan 26, 2009

Appl. No.:

12/359434

Inventors:

Michael P Chudzik - Danbury CT, US
Michael A Gribelyuk - Stamford CT, US
Rashmi Jha - Toledo OH, US
Renee T Mo - Briarcliff Manor NY, US
Naim Moumen - Walden NY, US
Keith Kwong Hon Wong - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/3205

US Classification:

438585, 257E21159, 257E29158

Abstract:

A metal gate and high-k dielectric device includes a substrate, an interfacial layer on top of the substrate, a high-k dielectric layer on top of the interfacial layer, a metal film on top of the high-k dielectric layer, a cap layer on top of the metal film and a metal gate layer on top of the cap layer. The thickness of the metal film and the thickness of the cap layer are tuned such that a target concentration of a cap layer material is present at an interface of the metal film and the high-k dielectric layer.

US Patent:

7838908, Nov 23, 2010

Filed:

Jan 26, 2009

Appl. No.:

12/359520

Inventors:

Unoh Kwon - Fishkill NY, US
Siddarth A. Krishnan - Peekskill NY, US
Takashi Ando - Tuckahoe NY, US
Michael P. Chudzik - Danbury CT, US
Martin M. Frank - Dobbs Ferry NY, US
William K. Henson - Beacon NY, US
Rashmi Jha - Toledo OH, US
Yue Liang - Beacon NY, US
Vijay Narayanan - New York NY, US
Ravikumar Ramachandran - Pleasantville NY, US
Keith Kwong Hon Wong - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/10

US Classification:

257204, 257351, 257371, 257388, 257412, 257E27062

Abstract:

A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiOand alpha-silicon layers or a dBARC layer.

US Patent:

7915115, Mar 29, 2011

Filed:

Jun 3, 2008

Appl. No.:

12/132146

Inventors:

Michael P. Chudzik - Danbury CT, US
Rashmi Jha - Wappingers Falls NY, US
Naim Moumen - Walden NY, US
Keith Kwong Hon Wong - Wappingers Falls NY, US
Ying H. Tsang - Newburgh NY, US

Assignee:

International Business Machines Corporation - Armonk NY
Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 29/72

US Classification:

438216, 438703, 216 41, 216 49, 430322, 430329

Abstract:

Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i. e. , a mixture of nitrogen and hydrogen) (N/H) or ammonia (NH) may be used to remove the photoresist mask. With the use of the plasma nitrogen-hydrogen forming gas (N/H) or a plasma ammonia (NH), no apparent organic residual is observed.

US Patent:

7919379, Apr 5, 2011

Filed:

Sep 10, 2007

Appl. No.:

11/852906

Inventors:

Eduard A. Cartier - New York NY, US
Rashmi Jha - Wappingers Falls NY, US
Sivananda Kanakasabapathy - Niskayuna NY, US
Xi Li - Somers NY, US
Renee T. Mo - Briarcliff Manor NY, US
Vijay Narayanan - New York NY, US
Vamsi Paruchuri - Albany NY, US
Mark T. Robson - Danbury CT, US
Kathryn T. Schonenberg - Wappingers Falls NY, US
Michelle L. Steen - Danbury CT, US
Richard Wise - Newburgh NY, US
Ying Zhang - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00
H01L 21/336

US Classification:

438302, 438304, 438305, 438306, 438592, 257316, 257320, 257387, 257E21202, 257E21205, 257E21444

Abstract:

The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.

US Patent:

7943457, May 17, 2011

Filed:

Apr 14, 2009

Appl. No.:

12/423236

Inventors:

Michael P. Chudzik - Danbury CT, US
Wiliam K. Henson - Beacon NY, US
Rashmi Jha - Toledo OH, US
Yue Liang - Beacon NY, US
Ravikumar Ramachandran - Pleasantville NY, US
Richard S. Wise - Newburgh NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/336

US Classification:

438199, 438142, 438151, 438157, 438283, 438798, 257407

Abstract:

The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.

US Patent:

7947549, May 24, 2011

Filed:

Feb 26, 2008

Appl. No.:

12/037158

Inventors:

Michael P Chudzik - Danbury CT, US
Rashmi Jha - Beacon NY, US
Siddarth A Krishnan - Peekskill NY, US
Naim Moumen - Walden NY, US
Vijay Narayanan - New York NY, US
Vamsi Paruchuri - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8238

US Classification:

438216, 438199, 257369, 257E21632

Abstract:

CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.

US Patent:

7955926, Jun 7, 2011

Filed:

Mar 26, 2008

Appl. No.:

12/055682

Inventors:

Wesley C. Natzle - New Paltz NY, US
Renee T. Mo - Briarcliff Manor NY, US
Rashmi Jha - Wappingers Falls NY, US
Kathryn T. Schonenberg - Wappingers Falls NY, US
Richard A. Conti - Katonah NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00

US Classification:

438240, 438197, 257310, 257544

Abstract:

In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric.

US Patent:

8053306, Nov 8, 2011

Filed:

Dec 13, 2007

Appl. No.:

11/955491

Inventors:

Rick Carter - Hopewell Junction NY, US
Michael P. Chudzik - Danbury CT, US
Rashmi Jha - Wappingers Falls NY, US
Naim Moumen - Walden NY, US

Assignee:

International Business Machines Corporation - Armonk NY
Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/8238
H01L 27/092

US Classification:

438228, 438224, 257371, 257E21632, 257E21639

Abstract:

A PFET having tailored dielectric constituted in part by an NFET threshold voltage (Vt) work function tuning layer in a gate stack thereof, related methods and integrated circuit are disclosed. In one embodiment, the PFET includes an n-type doped silicon well (N-well), a gate stack including: a doped band engineered PFET threshold voltage (Vt) work function tuning layer over the N-well; a tailored dielectric layer over the doped band engineered PFET Vt work function tuning layer, the tailored dielectric layer constituted by a high dielectric constant layer over the doped band engineered PFET Vt work function tuning layer and an n-type field effect transistor (NFET) threshold voltage (Vt) work function tuning layer over the high dielectric constant layer; and a metal over the NFET Vt work function tuning layer.