Rajendran V Panda

US Patent:

6819538, Nov 16, 2004

Filed:

May 15, 2001

Appl. No.:

09/858126

Inventors:

David T. Blaauw - Austin TX
Rajendran V. Panda - Round Rock TX
Rajat Chaudhry - Austin TX
Vladimir P. Zolotov - Cedar Park TX

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H02H 300

US Classification:

361 90, 361 18, 361 58, 361100

Abstract:

The present invention relates generally methods and apparatus for controlling current demand in an integrated circuit. One embodiment relates to a method that includes detecting if a supply voltage overshoot or a undershoot is present or anticipated, and if detected, controlling current consumed by a power consumption circuitry to ensure that the power supply voltage remains within acceptable levels. Other embodiments relate to an integrated circuit having a capacitive decoupling structure, power consumption circuitry, and power consumption control circuitry for controlling current consumed by at least a portion of the power consumption circuitry. Therefore, embodiments of the invention relate to monitoring and controlling power consumption (i. e. current demand) of a power consumption circuit (such as an integrated circuit) in order to prevent devastating supply voltage undershoots, overshoots, and oscillations.

US Patent:

7093223, Aug 15, 2006

Filed:

Nov 26, 2002

Appl. No.:

10/304423

Inventors:

Murat R. Becer - Round Rock TX, US
Ilan Algor - Ganei Tikva, IL
Rajendran V. Panda - Round Rock TX, US
David T. Blaauw - Ann Arbor MI, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 17/50

US Classification:

716 13, 716 10, 716 14

Abstract:

A method for designing and routing circuitry having reduced cross talk. Early noise analysis () is performed after global routing () but before detailed routing () in order to repair problems () before detailed routing () is performed. In one embodiment, the early noise analysis () is preceded by probabilistic extraction (). In one embodiment, probabilistic extraction () includes determining a probability of occurrence for each configuration in a predetermined set of configurations (). Probabilistic capacitance extraction is then performed (). A probabilistic distributed coupled RC network is constructed using the extracted capacitances (). In one embodiment, probabilistic extraction () includes estimating aggressor strength () using the probabilistic distributed coupled RC network.

US Patent:

7127384, Oct 24, 2006

Filed:

Aug 27, 2002

Appl. No.:

10/333432

Inventors:

Vladimir P. Zolotov - Cedar Park TX, US
Rajendran V. Panda - Round Rock TX, US
Sergey V. Gavrilov - Moscow, RU
Alexey L. Glebov - Moskovskay Oblast, RU
Yury B. Egorov - Moscow, RU
Dmitry Y. Nadexhin - Moscow, RU

Assignee:

Freescale semiconductor, Inc. - Austin TX

International Classification:

G06F 17/50

US Classification:

703 14

Abstract:

A fast transient simulator of SOI MOS circuits uses fast and accurate SOI transistor table models. The simulator uses a representation of a circuit with partitions. Each of partitions is simulated separately for a short time step by numerically solving differential equations describing its transient behavior. Behavior of the whole circuit is simulated in an event driven way where each event corresponds to an integration time step for each partition. Instead of body voltage, the simulator implements a transformation and uses body charge as an independent variable in order to obtain high accuracy and high speed of simulation. Construction of SOI transistor table models results in speed and accuracy enhancements. This transformation allows the reduction of the number of table dimensions exploiting the fact that SOI transistor backgate capacitance is approximately constant.

US Patent:

7149674, Dec 12, 2006

Filed:

May 30, 2000

Appl. No.:

09/580854

Inventors:

Supamas Sirichotiyakul - Austin TX, US
David T. Blaauw - Austin TX, US
Timothy J. Edwards - Austin TX, US
Chanhee Oh - Cibolo TX, US
Rajendran V. Panda - Round Rock TX, US
Judah L. Adelman - Shimshon, IL
David Moshe - Haifa, IL
Abhijit Dharchoudhury - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 17/50

US Classification:

703 15, 716 2, 716 6, 716 11, 327534

Abstract:

A method of improving performance of a dual Vintegrated circuit is disclosed in which a first value is calculated for each transistor of the integrated circuit that has a first threshold voltage level. The first value is based at least in part on delay and leakage of the circuit calculated as if the corresponding transistor had a second threshold voltage level. One transistor is then selected based on the first values. The threshold voltage of the selected transistor is then set to the second threshold voltage level. The area of at least one transistor within the circuit is modified, and the circuit is then sized to a predetermined area. The process may then be repeated if the circuit performance fails to meet a defined constraint. In one embodiment, the performance determination includes calculating the leakage current of a set of DC-connected components into which the circuit is partitioned, determining dominant logic states for each of the components, estimating the leakage of each of these dominant logic states, and summing the weighted averages of these dominant components based on state probabilities.

US Patent:

7251797, Jul 31, 2007

Filed:

Nov 22, 2004

Appl. No.:

10/994858

Inventors:

Murat R. Becer - Cedar Park TX, US
Ilan Algor - Gnei-Tikva, IL
Amir Grinshpon - Tel Aviv, IL
Rafi Levy - Tel-Aviv, IL
Chanhee Oh - Austin TX, US
Rajendran V. Panda - Round Rock TX, US
Vladimir P. Zolotov - Putnam Valley NY, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 17/50

US Classification:

716 6, 716 2

Abstract:

Processes and systems () for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise () and path based delay noise () analysis. Effective delta delay determines an impact () on victim timing of an action by aggressors that occur during a region () where victim and aggressor timing windows overlap and determines an effective delta delay corresponding to any portion of the impact on victim timing that extends beyond the victim timing window. The effective delta delay is used to adjust the victim timing window. Path based delta delay determines an uncertainty () in a switching time corresponding to a particular path for a victim resulting from an action (switching) by aggressors that occurs at the switching time , i. e. during a switching time window (a to a+u) () when uncertainty is included.

US Patent:

7571404, Aug 4, 2009

Filed:

Dec 5, 2006

Appl. No.:

11/566915

Inventors:

Min Zhao - College Station TX, US
Rajendran V. Panda - Round Rock TX, US
Savithri Sundareswaran - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716 5, 716 1, 716 2, 716 6, 716 18, 703 13, 703 14

Abstract:

A semiconductor power network decoupling capacitance (decap) budgeting problem is formulated to minimize the total decap to be added to the network subject to voltage constraints on the network nodes of a semiconductor circuit design. Voltage constraints on the decap to be added are taken into consideration such that the decap can be distributed throughout a hot spot region of the semiconductor circuit design and not be limited to placement at a single location in the circuit. Dynamic network voltages are at all times maintained greater than a user-specified threshold voltage level.

US Patent:

7698677, Apr 13, 2010

Filed:

Mar 31, 2007

Appl. No.:

11/731028

Inventors:

Min Zhao - College Station TX, US
Rajendran Panda - Round Rock TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 17/50

US Classification:

716 10, 716 2, 716 13, 716 14

Abstract:

A semiconductor power network () decoupling capacitance (decap) budgeting problem is co-optimized with a wiring enhancement problem, wherein the solution is formulated to minimize the total decap to be added or wiring changes (addition of wires ()) to be made to the network (). Voltage constraints, available white space and other constraints determine the amount of decap to be added. Wire enhancements and/or added decap can be distributed throughout a violation region () of the semiconductor circuit () design to reduce dynamic supply voltage noise so that dynamic network voltages are at all times maintained greater than a user-specified threshold voltage level ().

US Patent:

60744294, Jun 13, 2000

Filed:

Mar 3, 1997

Appl. No.:

8/805865

Inventors:

Satyamurthy Pullela - Austin TX
Stephen C. Moore - Austin TX
David Blaauw - Austin TX
Rajendran Panda - Austin TX
Gopalakrishnan Vijayan - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1750

US Classification:

716 6

Abstract:

Speed, size, and power trade-offs of a VLSI combinational circuit are optimized through iterative restructuring. First, timing analysis for the circuit is performed (102) to find the critical path through the circuit (104). Then, a gate is selected from the critical path (106), and a window is contracted around the gate (108). Within the window, alternate structures are constructed (110) and sized (112). The best alternative is substituted into the window (114), and the new circuit is resized (116). If the new circuit is not an improvement over the old (118), then the original window is replaced (120). In any case, this is repeated for each gate in the circuit (124). The entire process is then repeated until either user constraints are met, or the circuit doesn't change (122).