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Raj R Varada

age ~53

from Fremont, CA

Also known as:
  • Raj Ramachandran Varada
  • Raj Varada
  • Aj Varada

Raj Varada Phones & Addresses

  • Fremont, CA
  • 6248 Rubicon Ave, Newark, CA 94560 • 5107906350
  • Sunnyvale, CA
  • Wappingers Falls, NY
  • 1912 Tradan Dr, San Jose, CA 95132 • 4087198907
  • Alameda, CA
  • 3229 Mackenzie Pl, Fremont, CA 94536 • 5592731108

Work

  • Company:
    Intel corporation
    1999 to 2013
  • Position:
    Senior principal engineer

Education

  • Degree:
    Bachelor's degree or higher

Skills

Place & Route • Physical Synthesis • IEEE • VLSI • Timing • Processors • Electrical Engineering • System Design • Physical Design • Timing Closure • Static Timing Analysis • Logic Synthesis • EDA • SoC • ASIC

Awards

SNUG SV Tiger Team 2011 • ISSCC 2009. Beatrice Award Winner for Outstanding Editorial Paper

Interests

Recent Papers Published: * Re-timing Tra...

Industries

Semiconductors

Resumes

Raj Varada Photo 1

Senior Principal Engineer At Intel Corporation

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Position:
Senior Principal Engineer at Intel Corporation
Location:
San Francisco Bay Area
Industry:
Semiconductors
Work:
Intel Corporation since 1999
Senior Principal Engineer

Texas Instruments 1998 - 1999
Senior CAD Architect

IBM Design Automation Lab 1996 - 1998
Staff Engineer

Semiconductor Complex Limited 1990 - 1996
Senior Engineer
Skills:
Place & Route
Physical Synthesis
IEEE
VLSI
Timing
Processors
Electrical Engineering
System Design
Physical Design
Timing Closure
Static Timing Analysis
Logic Synthesis
EDA
SoC
ASIC
Interests:
Recent Papers Published: * Re-timing Trade-off in High Performance Graphics Designs, DAC 2010 * Superblock: A Method for Synthesizing Large High Performance Designs without Hierarchy Limits, DAC 2010 * A 45nm 8-Core Enterprise Xeon® Processor, JSSC Jan 2010 * Automated Pseudo-Flat Design Methodology for Register Arrays, DAC 2009 * Monte Carlo Techniques for Physical Synthesis Design Convergence Exploration, DAC 2009 * A 45nm 8-Core Enterprise Xeon® Processor, ISSCC 2009. Beatrice Award Winner for Outstanding Editorial Paper * Routing and DFM, at DAC 2008 * Practical DFM: Addressing Variations – During Layout, Post-Layout and Post-Silicon, ICCAD 2007 Tutorial * A 65-nm Dual-Core Multithreaded Xeon Processor With 16-MB L3 Cache, IEEE JSSC, Jan 2007 * SOC Design Challenges in a Multi-threaded 65nm Dual Core Xeon® MP Processor, IEEE SOCC-2006 * Design and Integration Methods for a Multi-threaded Dual Core 65nm Xeon® Processor, ICCAD 2006
Honor & Awards:
SNUG SV Tiger Team 2011 ISSCC 2009. Beatrice Award Winner for Outstanding Editorial Paper

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Raj Varada

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Raj Varada Photo 3

Varada Raj

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Myspace

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Raj Varada

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Gender:
Male
Birthday:
1911
Raj Varada Photo 5

Raj Varada

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Locality:
Singapore
Gender:
Male
Birthday:
1911

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