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Phonesavanh Saopraseuth

from Clackamas, OR

Also known as:
  • Phonesavanh L Saopraseuth
  • Phonesava Saopraseuth
  • Ponce P Saopraseuth
Phone and address:
13560 SE Taralon Dr, Happy Valley, OR 97015
5035588472

Phonesavanh Saopraseuth Phones & Addresses

  • 13560 SE Taralon Dr, Clackamas, OR 97015 • 5035588472
  • 800 Roberts Ave, Gresham, OR 97030 • 5034651122
  • Colorado Springs, CO
  • 13560 SE Taralon Dr, Clackamas, OR 97015

Us Patents

  • Local Interconnect

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  • US Patent:
    6927494, Aug 9, 2005
  • Filed:
    Mar 27, 2003
  • Appl. No.:
    10/400279
  • Inventors:
    Derryl D. J. Allman - Camas WA, US
    James R. Hightower - Fort Collins CO, US
    Phonesavanh Saopraseuth - Gresham OR, US
  • Assignee:
    LSI Logic Corporation - Milpitas CA
  • International Classification:
    H01L023/48
  • US Classification:
    257758, 257762, 438622
  • Abstract:
    A method for forming the electrical interconnect levels and circuit elements of an integrated circuit is provided by the present invention. The method utilizes a relatively thin layer of conductive material having a higher resistance than the metal typically used to form electrical interconnections, such as titanium nitride, to provide relatively short local interconnections between circuit elements of the integrated circuit. In addition, this same thin layer of conductive material is used to form macro elements such as capacitors, resistors, and fuses in the integrated circuit. By allowing the removal of space consuming transverse electrical interconnect lines from the interconnect levels, the present invention increases the routing density of the electrical interconnect levels. Furthermore, by allowing these local electrical interconnections to be produced during the same manufacturing step as the macro elements of the integrated circuit, the method of the present invention tends to reduce the number of steps required to produce an integrated circuit.
  • Local Interconnect

    view source
  • US Patent:
    6576544, Jun 10, 2003
  • Filed:
    Sep 28, 2001
  • Appl. No.:
    09/966464
  • Inventors:
    Derryl D. J. Allman - Camas WA
    James R. Hightower - Fort Collins CO
    Phonesavanh Saopraseuth - Gresham OR
  • Assignee:
    LSI Logic Corporation - Milpitas CA
  • International Classification:
    H01L 214763
  • US Classification:
    438622, 438687
  • Abstract:
    A method for forming the electrical interconnect levels and circuit elements of an integrated circuit is provided by the present invention. The method utilizes a relatively thin layer of conductive material having a higher resistance than the metal typically used to form electrical interconnections, such as titanium nitride, to provide relatively short local interconnections between circuit elements of the integrated circuit. In addition, this same thin layer of conductive material is used to form macro elements such as capacitors, resistors, and fuses in the integrated circuit. By allowing the removal of space consuming transverse electrical interconnect lines from the interconnect levels, the present invention increases the routing density of the electrical interconnect levels. Furthermore, by allowing these local electrical interconnections to be produced during the same manufacturing step as the macro elements of the integrated circuit, the method of the present invention tends to reduce the number of steps required to produce an integrated circuit.

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