Philip S Heidelberger

US Patent:

6381586, Apr 30, 2002

Filed:

Dec 10, 1998

Appl. No.:

09/209245

Inventors:

Paul Glasserman - New York NY
Philip Heidelberger - Cortlandt Manor NY
Nayyar P. Shahabuddin - Nanuet NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1760

US Classification:

705 36, 705 35

Abstract:

A computer implemented method prices derivative securities (for example, options) by selecting an importance sampling (IS) distribution and combining the chosen IS distribution with stratified sampling. The process consists of the steps of choosing an importance sampling distribution and combining the chosen importance sampling with stratification or Quasi-Monte Carlo (QMC) simulation. In the first step, an importance sampling distribution is chosen. In the second step, the chosen importance sampling is combined with stratification or Quasi-Monte Carlo sequencing. The pricing of many types of securities reduces to one of estimating an expectation of a real-valued function of some random variables.

US Patent:

6539460, Mar 25, 2003

Filed:

Jan 19, 2001

Appl. No.:

09/765563

Inventors:

Vittorio Castelli - Croton-on-Hudson NY
Peter A. Franaszek - Mt. Kisco NY
Philip Heidelberger - Cortlandt Manor NY
John T. Robinson - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711154, 711112, 711114, 710 68

Abstract:

A computing system includes a storage server having a memory organization that includes a compressed memory device for storing sectors, each sector having a sector data portion and associated header and trailers, either attached by the hosts or by components of the computing system. The compressed memory device comprises a memory directory and a plurality of fixed-size blocks. The system implements a methodology for detaching headers and trailers from sectors before storing the sectors in the memory, and storing the headers and trailers in the memory disk cache, separate from the sector data portion; and, reattaching headers and trailers to sector data portions when the sectors are sent from the memory to a host or to a mass storage device. The header and trailer data are managed through the same memory directory used to manage the compressed main memory. The process of detaching headers and trailers from sectors for separate storage results in increased efficacy of data compression, thus yielding better compression ratios, and decreased memory traffic generated by host reads, host writes, cache stages and cache destages.

US Patent:

6810495, Oct 26, 2004

Filed:

Mar 30, 2001

Appl. No.:

09/820611

Inventors:

Vittorio Castelli - Croton-on-Hudson NY
Richard E. Harper - Chapel Hill NC
Philip Heidelberger - Cortlandt Manor NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

714 47, 714 38

Abstract:

A method (and computer system in which at least one software component thereof is restarted based on projection of resource exhaustion), for selecting the most suitable projection method from among a class of projection methods, includes providing M fitting modules which take measured symptom data associated with the system as input and produce M scores, wherein M is an integer, selecting the fitting module producing the best score, and from the selected module, producing a prediction of the resource exhaustion time.

US Patent:

7024512, Apr 4, 2006

Filed:

Feb 10, 1998

Appl. No.:

09/021333

Inventors:

Peter Anthony Franaszek - Mount Kisco NY, US
Philip Heidelberger - Peekskill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00
G06F 9/00

US Classification:

711100, 711154, 711170, 711104, 707101, 704500

Abstract:

An improved method, system, and a computer program storage device (e. g. , including software embodied on a magnetic, electrical, optical, or other storage device) for management of compressed main memory allocation and utilization which can avoid system abends or inefficient operation that would otherwise result. One feature reduces (and ultimately eliminates) all unessential processing as the amount of available storage decreases to a point low enough to threaten a system abend. In another example, the amount of current memory usage is determined as well as one or more of: an estimate of an amount of allocated but unused memory; a determination of the amount of memory required for outstanding I/O requests. The compressed memory is managed as a function of the current memory usage and one or more of the other measured or estimated quantities. The compressed memory can be managed by maintaining a set of dynamic thresholds; estimating the amount of storage that can easily be freed (used but available) and the amount of storage that is committed (allocated but unused).

US Patent:

7039769, May 2, 2006

Filed:

May 30, 2002

Appl. No.:

10/158534

Inventors:

Vittorio Castelli - Croton-on-Hudson NY, US
Peter A. Franaszek - Mount Kisko NY, US
Philip Heidelberger - Cortlandt Manor NY, US
John Timothy Robinson - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/06

US Classification:

711147, 709215

Abstract:

In a computer system in which a plurality of hosts is connected through an interconnection network, an apparatus coupled to the interconnection network for allowing the plurality of hosts to share a collection of memory sectors, the memory sectors storing compressed data, is provided. The apparatus includes a network adapter for coupling the apparatus to the interconnection network; a memory for storing the collection of memory sectors; and control logic for managing the memory, the control logic including a memory compressor/decompressor. The memory further includes a directory for translating real addresses of at least one host to an address in the apparatus. A method for managing a number of memory sectors used by each host and a method for translating a real address specified by at least one host into a real address of the apparatus is also provided.

US Patent:

7149920, Dec 12, 2006

Filed:

Sep 30, 2003

Appl. No.:

10/674952

Inventors:

Matthew A. Blumrich - Ridgefield CT, US
Dong Chen - Croton On Hudson NY, US
Alan G. Gara - Mount Kisco NY, US
Philip Heidelberger - Cortlandt Manor NY, US
Dirk I. Hoenicke - Ossining NY, US
Pavlos M. Vranas - Bedford Hills NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00
G06F 11/07

US Classification:

714 4, 714 23, 714 24

Abstract:

Disclosed are an error recovery method and system for use with a communication system having first and second nodes, each of said nodes having a receiver and a sender, the sender of the first node being connected to the receiver of the second node by a first cable, and the sender of the second node being connected to the receiver of the first node by a second cable. The method comprising the step of after one of the nodes detects an error, both of the nodes entering the same defined state. In particular, the receiver of the first node enters an error state, stays in the error state for a defined period of time T, and, after said defined period of time T, enters a wait state. Also, the sender of the first node sends to the receiver of the second node an error message for a defined period of time Te, and after the defined period of time Te, the sender of the first node enters an idle state.

US Patent:

7174434, Feb 6, 2007

Filed:

Feb 25, 2002

Appl. No.:

10/468994

Inventors:

Matthias A. Blumrich - Ridgefield CT, US
Dong Chen - Croton On Hudson NY, US
Paul W. Coteus - Yorktown Heights NY, US
Alan G. Gara - Mount Kisco NY, US
Mark E. Giampapa - Irvington NY, US
Philip Heidelberger - Cortlandt Manor NY, US
Dirk Hoenicke - Ossining NY, US
Martin Ohmacht - Brewster NY, US
Todd E. Takken - Mount Kisco NY, US
Pavlos M. Vranas - Bedford Hills NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/12

US Classification:

711152, 711163

Abstract:

A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm.

US Patent:

7305487, Dec 4, 2007

Filed:

Feb 25, 2002

Appl. No.:

10/469001

Inventors:

Matthias A. Blumrich - Ridgefield CT, US
Dong Chen - Croton On Hudson NY, US
Paul W. Coteus - Yorktown Heights NY, US
Alan G. Gara - Mount Kisco NY, US
Mark E. Giampapa - Irvington NY, US
Philip Heidelberger - Cortlandt Manor NY, US
Todd E. Takken - Mount Kisco NY, US
Pavlos M. Vranas - Bedford Hills NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/173

US Classification:

709238, 709240, 709220, 370389, 370392

Abstract:

In a massively parallel computing system having a plurality of nodes configured in m multi-dimensions, each node including a computing device, a method for routing packets towards their destination nodes is provided which includes generating at least one of a 2m plurality of compact bit vectors containing information derived from downstream nodes. A multilevel arbitration process in which downstream information stored in the compact vectors, such as link status information and fullness of downstream buffers, is used to determine a preferred direction and virtual channel for packet transmission. Preferred direction ranges are encoded and virtual channels are selected by examining the plurality of compact bit vectors. This dynamic routing method eliminates the necessity of routing tables, thus enhancing scalability of the switch.