Peter J Windler

US Patent:

6566922, May 20, 2003

Filed:

Oct 29, 2001

Appl. No.:

10/052929

Inventors:

David L. Schell - Fort Collins CO
Peter J. Windler - Fort Collins CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11B 509

US Classification:

327156, 327159, 375376, 360 51

Abstract:

A circuit generally comprising a first circuit and a phase lock loop. The first circuit may be configured to (i) collect a plurality of samples per cycle during a plurality of cycles of an input signal and (ii) calculate a phase offset and a frequency offset for the input signal relative to a clock signal in response to the samples. The phase lock loop may be configured to (i) preset a phase error signal to the phase offset and a frequency error signal to the frequency offset and (ii) generate the clock signal in response to the phase error signal and the frequency error signal.

US Patent:

6614269, Sep 2, 2003

Filed:

Aug 13, 2002

Appl. No.:

10/217785

Inventors:

Kenneth G. Richardson - Erie CO
Peter Windler - Fort Collins CO

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H03D 100

US Classification:

327 58, 327 50

Abstract:

A polyphase amplitude detector for detecting the amplitude of a polyphase signal. The polyphase amplitude detector includes means for generating differential pair signals. The differential pair signals are buffered and amplified and then AC coupled to the amplitude detector. The amplitude detector detects the amplitude of each phase of the polyphase signal and generates output signals which are used to control the amplitude of the polyphase signal.

US Patent:

6650194, Nov 18, 2003

Filed:

Oct 25, 2000

Appl. No.:

09/696514

Inventors:

Robert Andrew Kertis - Rochester MN
Peter John Windler - Fort Collins CO

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03B 500

US Classification:

331117R, 331167, 331 57, 331 36 C

Abstract:

A circuit is disclosed which adjusts the phase of a signal within an LC sinusoidal or a ring or other capacitive oscillator. The circuit uses FETs as capacitors. The gates of the FETs are connected to the capacitive node of the oscillator. The variable voltage source changes the state of the FET from depleted to inverted mode or from inverted to depleted mode which in turn dramatically changes the capacitance of the FET. The change of state exists for only a few clock cycles, typically less than five cycles, so that only the capacitance within the oscillator is instantaneously affected which changes adds as incremental/decremental frequency to adjust only the phase of the oscillation frequency. In this fashion, the average oscillation frequency not affected.

US Patent:

7640463, Dec 29, 2009

Filed:

Jun 30, 2006

Appl. No.:

11/479839

Inventors:

Peter Windler - Fort Collins CO, US
Richard Lim - Fort Collins CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G06F 11/00

US Classification:

714707, 714700, 714704, 714709, 714713, 714715, 714721, 714731, 714744, 714712, 714 30, 714 43, 375224, 375355, 375371, 375293, 375317, 327 73, 386 89, 702 89, 702125

Abstract:

In a high-speed serial link, an eye finder diagnostic circuit has improved performance by being on-chip with the existing capture latch(es) of a receive equalizer. The eye finder circuit employs an additional capture latch with its input tied to the same input node as the existing capture latch(es) of a receive equalizer. The additional capture latch has a clock input and reference voltage input. The clock input is adjusted through a phase interpolator (or variable delay line) while the reference voltage input is adjusted by a voltage generator. A digital post processing circuit then compares the output of the additional capture latch with the output of the other existing capture latch(es), in order to determine the receive eye opening. The horizontal eye opening is measured by changing the phase of the additional capture latch through the phase interpolator, while the vertical eye opening is measured by changing the reference voltage of the voltage generator of the additional capture latch. The eye finder circuit, being on-chip and in-line with existing capture latch(es), employs a minimum of power, minimum of area, and minimizes the extra loading to the existing equalizer output.

US Patent:

7668239, Feb 23, 2010

Filed:

Sep 19, 2006

Appl. No.:

11/523784

Inventors:

Mark J. Marlett - Livermore CA, US
Mark Rutherford - Wellington CO, US
Peter Windler - Fort Collins CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H03K 7/08
H03K 3/017

US Classification:

375238, 327172

Abstract:

An improved method and apparatus for transmitting digital signals in a communications channel by compensating for distortions due to attenuation of high frequency components suffered by the digital signals. In a preferred embodiment, the digital signals are pulses and the compensation is performed at the transmitter without the need for an emphasis driver, by widening the pulses to compensate for the distortion in the channel that results in narrowing of the pulses incurred in the channel. The resulting pulse train is pre-compensated for the distortions caused by the communications channel. The amount of pre-compensation can be determined statically or dynamically.

US Patent:

7869498, Jan 11, 2011

Filed:

Feb 21, 2007

Appl. No.:

11/709568

Inventors:

Yi Zeng - Fremont CA, US
Freeman Zhong - San Ramon CA, US
Peter Windler - Fort Collins CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H03H 7/40

US Classification:

375233, 375229, 375230, 375231, 375232

Abstract:

Low power decision feedback equalization (DFE) through applying DFE data to input data in a data latch is disclosed. In one embodiment, a decision feedback equalization (DFE) system to remove a post cursor intersymbol interference (ISI) through feeding back previous data scaled with adaptive weights to the DFE system, with each slice of the DFE system may include a first set of decision feedback digital to analog converters (DACs) to generate a first DFE data obtained through the feeding back the previous data scaled with the adaptive weights and a first data latch to generate an output data of the each slice through applying the first DFE data to an input data of the each slice in the first data latch to remove a first delay caused by performing the applying the first DFE data to the input data of the each slice outside of the first data latch.

US Patent:

8437388, May 7, 2013

Filed:

Nov 19, 2010

Appl. No.:

12/949838

Inventors:

Yi Zeng - Fremont CA, US
Freeman Zhong - San Ramon CA, US
Peter Windler - Fort Collins CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H03H 7/40

US Classification:

375233, 375232, 326 46

Abstract:

Data latch circuit and method of low power decision feedback equalization (DFE) system is disclosed. In one embodiment, the data latch circuit of the of a decision feedback equalization (DFE) system includes a first parallel n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pair to input a differential input voltage. The data latch circuit also includes a second parallel NMOS pair coupled to the first parallel NMOS pair to input a decision feedback equalization (DFE) voltage. The data latch circuit further includes a cross-coupled PMOS pair to generate a positive feedback to the first parallel NMOS pair and/or the second parallel NMOS pair. In addition, the data latch circuit includes a cross-coupled NMOS pair to escalate the positive feedback. Furthermore the data latch circuit includes a latching circuit to generate a signal data based on the sinking of a current at an input of the latching circuit and/or the positive feedback.

US Patent:

20030001626, Jan 2, 2003

Filed:

Jun 28, 2001

Appl. No.:

09/894265

Inventors:

Robert Kertis - Rochester MN, US
Peter Windler - Fort Collins CO, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

H03K005/153

US Classification:

327/078000

Abstract:

A circuit is disclosed which uses less power and is responsive to high frequencies which can detect if a signal has sufficient amplitude. The signal of interest is input to an active semiconductor device. The other inputs to the active device are set by the value of the amplitude which the signal must be less than/greater than. The circuit is especially useful in an oscillator which generates high frequency clock signals to determine if the clock signals have sufficient amplitude to drive the electronics.