Paul G Sherer

US Patent:

6434165, Aug 13, 2002

Filed:

Aug 19, 1998

Appl. No.:

09/136795

Inventors:

Paul Sherer - Danville CA
Kenneth Araujo - Sunnyvale CA
Peter Si-Sheng Wang - Cupertino CA

Assignee:

3Com Corporation - Santa Clara CA

International Classification:

H04J 316

US Classification:

370465, 714758

Abstract:

A communications network system that transmits and receives communication frames that include a transmission status section that indicates a communication frame transmission is aborted. In one embodiment, a transmission status section includes a cyclical redundancy check value that is non-matching with the information in the communication frame. For example, a non-matching cyclical redundancy check value is created by generating a ones compliment of a CRC calculated based upon the information within a communication frame. The communication network includes a wireless network, a wired network (e. g. , an Ethernet network) and a data cable system that transmits a data over cable media access control (MAC) frame with an Ethernet/[ISO8802-3] type packet protocol data unit payload.

US Patent:

7899937, Mar 1, 2011

Filed:

Jan 21, 2000

Appl. No.:

09/488942

Inventors:

Richard Hausman - Soquel CA, US
Paul William Sherer - Sunnyvale CA, US
James P. Rivers - Sunnyvale CA, US
Cynthia Zikmund - Boulder Creek CA, US
Glenn W. Connery - Sunnyvale CA, US
Niles E. Strohl - Tracy CA, US
Richard S. Reid - Mountain View CA, US

Assignee:

U.S. Ethernet Innovations, LLC - Tyler TX

International Classification:

G06F 15/16
G06F 3/00
G06F 9/44
G06F 9/46
G06F 13/00

US Classification:

709250, 719321, 719327

Abstract:

In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

US Patent:

8239580, Aug 7, 2012

Filed:

Nov 4, 2010

Appl. No.:

12/939604

Inventors:

Richard Hausman - Soquel CA, US
Paul William Sherer - Sunnyvale CA, US
James P. Rivers - Sunnyvale CA, US
Cynthia Zikmund - Boulder Creek CA, US
Glenn W. Connery - Sunnyvale CA, US
Niles E. Strohl - Tracy CA, US
Richard S. Reid - Mountain View CA, US

Assignee:

U.S. Ethernet Innovations, LLC - Tyler TX

International Classification:

G06F 15/16
G06F 3/00
G06F 9/44
G06F 9/46
G06F 13/00

US Classification:

709250, 719321, 719327

Abstract:

In a Local Area Network (LAN) system, an Ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

US Patent:

61122521, Aug 29, 2000

Filed:

Feb 23, 1998

Appl. No.:

9/028088

Inventors:

Richard Hausman - Soquel CA
Paul William Sherer - Sunnyvale CA
James P. Rivers - Sunnyvale CA
Cynthia Zikmund - Boulder Creek CA
Glenn W. Connery - Sunnyvale CA
Niles E. Strohl - Tracy CA
Richard S. Reid - Mountain View CA

Assignee:

3Com Corporation - Santa Clara CA

International Classification:

G06F 1300
G06F 1332

US Classification:

709250

Abstract:

In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

US Patent:

54855845, Jan 16, 1996

Filed:

Jan 17, 1995

Appl. No.:

8/374491

Inventors:

Richard Hausman - Soquel CA
Paul W. Sherer - Sunnyvale CA
James P. Rivers - Sunnyvale CA
Cynthia Zikmund - Boulder Creek CA
Glenn W. Connery - Sunnyvale CA
Niles E. Strohl - Tracy CA
Richard S. Reid - Mountain View CA

Assignee:

3Com Corporation - Santa Clara CA

International Classification:

G06F 1300
G06F 1332

US Classification:

395842

Abstract:

In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

US Patent:

54209870, May 30, 1995

Filed:

Jul 19, 1993

Appl. No.:

8/093380

Inventors:

Richard S. Reid - Mountain View CA
Niles Strohl - Tracy CA
Glenn W. Connery - Sunnyvale CA
Paul W. Sherer - Sunnyvale CA
James P. Rivers - Sunnyvale CA

Assignee:

3 COM Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

395325

Abstract:

In a computer system having a central processing unit which employs software drivers as part of a host for controlling peripheral units and including a bus for connecting with adapters for the peripheral units, wherein each adapter has distributed intelligence means for interpreting simple command information and a nonvolatile storage element for storing default configuration information, including a default port address for communication, a method is provided for configuring such intelligent adapters connected to the bus. The method includes initializing the intelligent adapters by applying power to the bus or by issuing a global reset signal and causing a driver to be loaded by the central processing unit so that the host broadcasts a start key via a sequence of write commands via the bus to any adapters on the bus and to elicit responses from the intelligent adapters in an interactive manner to narrow communication between the intelligent adapters and the host to a single intelligent adapter without first specifying a unique port address. The narrowing process involves causing the intelligent adapters to first rank themselves for communication with the host by referring to unique ordered value information, e. g. , an identification serial number, stored in the nonvolatile storage element, such as an EEPROM element, placed on the adapter.

US Patent:

58729208, Feb 16, 1999

Filed:

Jul 18, 1995

Appl. No.:

8/503797

Inventors:

Richard Hausman - Soquel CA
Paul William Sherer - Sunnyvale CA
James P. Rivers - Sunnyvale CA
Cynthia Zikmund - Boulder Creek CA
Glenn W. Connery - Sunnyvale CA
Niles E. Strohl - Tracy CA
Richard S. Reid - Mountain View CA

Assignee:

3Com Corporation - Santa Clara CA

International Classification:

G06F 1300
G06F 1332

US Classification:

3952008

Abstract:

In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter may also be programmed to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

US Patent:

54127823, May 2, 1995

Filed:

Jul 2, 1992

Appl. No.:

7/907946

Inventors:

Richard Hausman - Soquel CA
Paul W. Sherer - Sunnyvale CA
James P. Rivers - Sunnyvale CA
Cynthia Zikmund - Boulder Creek CA
Glenn W. Connery - Sunnyvale CA
Niles E. Strohl - Tracy CA
Richard S. Reid - Mountain View CA

Assignee:

3COM Corporation - Santa Clara CA

International Classification:

C06F 1300
C06F 1338

US Classification:

395250

Abstract:

In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter may also be programmed to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.