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Paul G Sherer

age ~63

from Palo Alto, CA

Also known as:
  • Paul Gray Sherer
  • Paul Sherer
  • Paul Sherer Gray
  • Sherer Gray Pal
360 Leland Ave, Palo Alto, CA 943064157718128

Paul Sherer Phones & Addresses

  • 360 Leland Ave, Palo Alto, CA 94306 • 4157718128
  • 175 Island Dr, Palo Alto, CA 94301 • 6503218855
  • 375 Island Dr, Palo Alto, CA 94301 • 6503218855
  • 2808 Vallejo St, San Francisco, CA 94123 • 4157714670 • 4157718128
  • Los Altos, CA
  • Honolulu, HI
  • Santa Clara, CA
  • Novato, CA
  • Houston, TX
  • Philadelphia, PA

Work

  • Company:
    3 com corp
  • Address:
    5400 Bayfront Plz # 1417, Santa Clara, CA 95054
  • Position:
    Cto
  • Industries:
    Book Printing

Us Patents

  • Method And System To Abort Data Communication Traffic In A Communication Network

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  • US Patent:
    6434165, Aug 13, 2002
  • Filed:
    Aug 19, 1998
  • Appl. No.:
    09/136795
  • Inventors:
    Paul Sherer - Danville CA
    Kenneth Araujo - Sunnyvale CA
    Peter Si-Sheng Wang - Cupertino CA
  • Assignee:
    3Com Corporation - Santa Clara CA
  • International Classification:
    H04J 316
  • US Classification:
    370465, 714758
  • Abstract:
    A communications network system that transmits and receives communication frames that include a transmission status section that indicates a communication frame transmission is aborted. In one embodiment, a transmission status section includes a cyclical redundancy check value that is non-matching with the information in the communication frame. For example, a non-matching cyclical redundancy check value is created by generating a ones compliment of a CRC calculated based upon the information within a communication frame. The communication network includes a wireless network, a wired network (e. g. , an Ethernet network) and a data cable system that transmits a data over cable media access control (MAC) frame with an Ethernet/[ISO8802-3] type packet protocol data unit payload.
  • Programmed I/O Ethernet Adapter With Early Interrupts For Accelerating Data Transfer

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  • US Patent:
    7899937, Mar 1, 2011
  • Filed:
    Jan 21, 2000
  • Appl. No.:
    09/488942
  • Inventors:
    Richard Hausman - Soquel CA,
    Paul William Sherer - Sunnyvale CA,
    James P. Rivers - Sunnyvale CA,
    Cynthia Zikmund - Boulder Creek CA,
    Glenn W. Connery - Sunnyvale CA,
    Niles E. Strohl - Tracy CA,
    Richard S. Reid - Mountain View CA,
  • Assignee:
    U.S. Ethernet Innovations, LLC - Tyler TX
  • International Classification:
    G06F 15/16
    G06F 3/00
    G06F 9/44
    G06F 9/46
    G06F 13/00
  • US Classification:
    709250, 719321, 719327
  • Abstract:
    In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
  • Programmed I/O Ethernet Adapter With Early Interrupts For Accelerating Data Transfer

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  • US Patent:
    8239580, Aug 7, 2012
  • Filed:
    Nov 4, 2010
  • Appl. No.:
    12/939604
  • Inventors:
    Richard Hausman - Soquel CA,
    Paul William Sherer - Sunnyvale CA,
    James P. Rivers - Sunnyvale CA,
    Cynthia Zikmund - Boulder Creek CA,
    Glenn W. Connery - Sunnyvale CA,
    Niles E. Strohl - Tracy CA,
    Richard S. Reid - Mountain View CA,
  • Assignee:
    U.S. Ethernet Innovations, LLC - Tyler TX
  • International Classification:
    G06F 15/16
    G06F 3/00
    G06F 9/44
    G06F 9/46
    G06F 13/00
  • US Classification:
    709250, 719321, 719327
  • Abstract:
    In a Local Area Network (LAN) system, an Ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
  • Programmed I/O Ethernet Adapter With Early Interrupt And Dma Control For Accelerating Data Transfer

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  • US Patent:
    61122521, Aug 29, 2000
  • Filed:
    Feb 23, 1998
  • Appl. No.:
    9/028088
  • Inventors:
    Richard Hausman - Soquel CA
    Paul William Sherer - Sunnyvale CA
    James P. Rivers - Sunnyvale CA
    Cynthia Zikmund - Boulder Creek CA
    Glenn W. Connery - Sunnyvale CA
    Niles E. Strohl - Tracy CA
    Richard S. Reid - Mountain View CA
  • Assignee:
    3Com Corporation - Santa Clara CA
  • International Classification:
    G06F 1300
    G06F 1332
  • US Classification:
    709250
  • Abstract:
    In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
  • Apparatus For Simulating A Stack Structure Using A Single Register And A Counter To Provide Transmit Status In A Programmed I/O Ethernet Adapter With Early Interrupts

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  • US Patent:
    54855845, Jan 16, 1996
  • Filed:
    Jan 17, 1995
  • Appl. No.:
    8/374491
  • Inventors:
    Richard Hausman - Soquel CA
    Paul W. Sherer - Sunnyvale CA
    James P. Rivers - Sunnyvale CA
    Cynthia Zikmund - Boulder Creek CA
    Glenn W. Connery - Sunnyvale CA
    Niles E. Strohl - Tracy CA
    Richard S. Reid - Mountain View CA
  • Assignee:
    3Com Corporation - Santa Clara CA
  • International Classification:
    G06F 1300
    G06F 1332
  • US Classification:
    395842
  • Abstract:
    In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
  • Method And Apparatus For Configuring A Selected Adapter Unit On A Common Bus In The Presence Of Other Adapter Units

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  • US Patent:
    54209870, May 30, 1995
  • Filed:
    Jul 19, 1993
  • Appl. No.:
    8/093380
  • Inventors:
    Richard S. Reid - Mountain View CA
    Niles Strohl - Tracy CA
    Glenn W. Connery - Sunnyvale CA
    Paul W. Sherer - Sunnyvale CA
    James P. Rivers - Sunnyvale CA
  • Assignee:
    3 COM Corporation - Santa Clara CA
  • International Classification:
    G06F 1300
  • US Classification:
    395325
  • Abstract:
    In a computer system having a central processing unit which employs software drivers as part of a host for controlling peripheral units and including a bus for connecting with adapters for the peripheral units, wherein each adapter has distributed intelligence means for interpreting simple command information and a nonvolatile storage element for storing default configuration information, including a default port address for communication, a method is provided for configuring such intelligent adapters connected to the bus. The method includes initializing the intelligent adapters by applying power to the bus or by issuing a global reset signal and causing a driver to be loaded by the central processing unit so that the host broadcasts a start key via a sequence of write commands via the bus to any adapters on the bus and to elicit responses from the intelligent adapters in an interactive manner to narrow communication between the intelligent adapters and the host to a single intelligent adapter without first specifying a unique port address. The narrowing process involves causing the intelligent adapters to first rank themselves for communication with the host by referring to unique ordered value information, e. g. , an identification serial number, stored in the nonvolatile storage element, such as an EEPROM element, placed on the adapter.
  • Programmed I/O Ethernet Adapter With Early Interrupts For Accelerating Data Transfer

    view source
  • US Patent:
    58729208, Feb 16, 1999
  • Filed:
    Jul 18, 1995
  • Appl. No.:
    8/503797
  • Inventors:
    Richard Hausman - Soquel CA
    Paul William Sherer - Sunnyvale CA
    James P. Rivers - Sunnyvale CA
    Cynthia Zikmund - Boulder Creek CA
    Glenn W. Connery - Sunnyvale CA
    Niles E. Strohl - Tracy CA
    Richard S. Reid - Mountain View CA
  • Assignee:
    3Com Corporation - Santa Clara CA
  • International Classification:
    G06F 1300
    G06F 1332
  • US Classification:
    3952008
  • Abstract:
    In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter may also be programmed to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
  • Programmed I/O Ethernet Adapter With Early Interrupts For Accelerating Data Transfer

    view source
  • US Patent:
    54127823, May 2, 1995
  • Filed:
    Jul 2, 1992
  • Appl. No.:
    7/907946
  • Inventors:
    Richard Hausman - Soquel CA
    Paul W. Sherer - Sunnyvale CA
    James P. Rivers - Sunnyvale CA
    Cynthia Zikmund - Boulder Creek CA
    Glenn W. Connery - Sunnyvale CA
    Niles E. Strohl - Tracy CA
    Richard S. Reid - Mountain View CA
  • Assignee:
    3COM Corporation - Santa Clara CA
  • International Classification:
    C06F 1300
    C06F 1338
  • US Classification:
    395250
  • Abstract:
    In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter may also be programmed to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

Wikipedia

Drew Major

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Major left Novell in 2003 and, with Paul Sherer (ex-3Com CTO responsible for Ethernet's success), founded Arroyo Video Solutions, which developed video ...

Name / Title
Company / Classification
Phones & Addresses
Paul Sherer
CTO
3 Com Corp
Book Printing
5400 Bayfront Plz # 1417, Santa Clara, CA 95054
Paul Sherer
Sherer Communications LLC
1226 Worchester Ct, Walnut Creek, CA 94596

Resumes

Paul Sherer Photo 1

Venture Partner At Matrix Partners

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Position:
Venture Partner at Matrix Partners
Location:
San Francisco Bay Area
Industry:
Venture Capital & Private Equity
Work:
Matrix Partners since Mar 2010
Venture Partner

Cisco Systems, Inc. Jul 2002 - Mar 2010
CTO, Video

Arroyo Video Solutions Jul 2002 - Aug 2006
CEO

Texas Pacific Group Aug 2001 - Dec 2002
Entrepreneur in Residence

Matrix Partners Aug 2001 - Jun 2002
Entrepreneur in Residence
Education:
University of Alabama in Huntsville 1981 - 1982
PhD, Electrical Engineering
University of Alabama 1977 - 1981
BSEE, Electrical Engineering
Skills:
Executive Management
Technology Strategy Development
New Venture Development
Cloud Computing
Security
Storage
Distributed Systems
IP
Mobile Applications
Mobile Technology
Ethernet
Start-ups
Business Development
Technology Product Development
Go-to-market Strategy
Strategic Alliances
Wireless
Routing
Strategic Partnerships
Product Management
VOD
Entrepreneurship
Mobile Devices
Strategy
Product Marketing
Paul Sherer Photo 2

Paul Sherer

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Location:
Palo Alto, California
Industry:
Venture Capital & Private Equity
Paul Sherer Photo 3

Paul Sherer

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Position:
Principal at Sherer Communications LLC
Location:
San Francisco Bay Area
Industry:
Public Relations and Communications
Work:
Sherer Communications LLC - San Francisco Bay Area since Apr 2013
Principal

Ogilvy Public Relations - San Francisco Bay Area Jan 2005 - Mar 2013
Senior Vice President and Group Director, West Coast Corporate Practice

Freelance Writer - Walnut Creek, Calif. Jun 2002 - Jan 2005
Freelance Writer

The Wall Street Journal Sep 1998 - May 2001
Staff Reporter, Money & Investing

The Asian Wall Street Journal Apr 1994 - Aug 1998
Staff Reporter, Bangkok Correspondent
Education:
Massachusetts Institute of Technology 1983 - 1988
Paul Sherer Photo 4

Paul Sherer

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Location:
San Francisco Bay Area
Industry:
Online Media
Paul Sherer Photo 5

Paul Sherer

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Location:
United States
Paul Sherer Photo 6

Paul Sherer

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Location:
United States
Paul Sherer Photo 7

Paul Sherer

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Location:
United States

Youtube

Paul Sherer....Golf Legend. The best swing in...

Golf Legend. The best swing in the business.

  • Category:
    Sports
  • Uploaded:
    03 Oct, 2011
  • Duration:
    2m 22s

Colleges of Terre Haute

Video made by Rose-Hulman students Philip Sherer, Paul McCulfor, and M...

  • Category:
    Education
  • Uploaded:
    03 Dec, 2008
  • Duration:
    10m 44s

Paul Sherer Interview (Re-Mix)

Visit JAZZY100.COM for more information.

  • Category:
    Entertainment
  • Uploaded:
    30 Aug, 2011
  • Duration:
    9m 59s

Googleplus

Paul Sherer Photo 8

Paul Sherer

Paul Sherer Photo 9

Paul Sherer

Education:
Clarion University of Pennsylvania - Political Science/Computer Science, Eisenhower High School
Relationship:
In_a_relationship
About:
Currently a Junior at Clarion University of Pennsylvania pursuing dual majors in Political Science and Computer Science with minors in Psychology and Spanish, Paul runs his own local web development a...
Paul Sherer Photo 10

Paul Sherer

Plaxo

Paul Sherer Photo 11

Paul Sherer

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Palo Alto, CAPartner at Noribachi Group
Paul Sherer Photo 12

Paul Sherer

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Just retired and finally have the time to enjoy doing all the things that work has prevented

Facebook

Paul Sherer Photo 13

Paul Sherer

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Paul Sherer Photo 14

Paul Sherer

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Paul Sherer Photo 15

Paul Sherer

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Paul Sherer Photo 16

Paul Bahauddin Sherer

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Paul Sherer Photo 17

Paul Sherer

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Paul Sherer Photo 18

Paul Sherer s

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Paul Sherer Photo 19

Paul Sherer

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Flickr


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