Paul H Ouyang

US Patent:

6347029, Feb 12, 2002

Filed:

Jul 2, 1999

Appl. No.:

09/346608

Inventors:

Paul H. Ouyang - San Jose CA
Joseph W. Ku - Palo Alto CA
Donald Liusie - San Jose CA

Assignee:

Dmel, Inc. - Santa Clara CA

International Classification:

H02H 300

US Classification:

361 939, 327309, 36518909

Abstract:

Current protection circuit has a comparator having a first terminal coupled to a reference voltage, a second terminal coupled to an output node, and an output for providing a control signal based on the inputs. Current protection circuit also has a transistor having a drain electrode coupled to a first predetermined voltage, a gate electrode, and a source electrode coupled to the output node. The transistor includes a current path between the drain electrode and the source electrode for conducting an amount of current that is dependent on the voltage applied to the gate electrode. Current protection circuit also has a fold-back circuit having a first input coupled to the output node for detecting changes in the output voltage, a second input coupled to the output of comparator for receiving the control signal, and a third input for selectively changing the voltage applied to the gate electrode based the control signal and the changes in the output voltage.

US Patent:

6351172, Feb 26, 2002

Filed:

Feb 29, 2000

Appl. No.:

09/515220

Inventors:

Paul H. Ouyang - San Jose CA
Joseph W. Ku - Palo Alto CA
Donald Liusie - San Jose CA

Assignee:

Dmel Inc. - Santa Clara CA

International Classification:

H03L 500

US Classification:

327333, 327112

Abstract:

A dynamic impedance adjustment circuit that reduces overshoot and undershoot noise while achieving fast slew rates. The dynamic impedance adjustment circuit has an output driver for selectively driving or drawing current providing source or sink current. The dynamic impedance adjustment circuit also has an a variable impedance output driver for selectively providing a dynamic current (source or sink) for a predetermined time after transitions from a logic low level to a logic high level or from a logic high level to a low logic level in the input signal. An impedance adjustment control circuit is coupled to the variable impedance output driver for automatically detecting the transitions in the input signal and for changing the impedance of the variable impedance output driver based on the input signal, enable signal, and the output node.

US Patent:

6396368, May 28, 2002

Filed:

Nov 10, 1999

Appl. No.:

09/438085

Inventors:

Tsung-Yuan Hsu - Westlake Village CA
Daniel J. Hyman - Cleveland OH
Robert Y. Loo - Agoura Hills CA
Paul Ouyang - San Jose CA
James H. Schaffner - Chatsworth CA
Adele Schmitz - Newbury Park CA
Robert N. Schwartz - Costa Mesa CA

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01P 110

US Classification:

333262, 200181, 200600

Abstract:

A microelectromechanical (MEM) switch is fabricated inexpensively by using processing steps which are standard for fabricating multiple metal layer integrated circuits, such as CMOS. The exact steps may be adjusted to be compatible with the process of a particular foundry, resulting in a device which is both low cost and readily integrable with other circuits. The processing steps include making contacts for the MEM switch from metal plugs which are ordinarily used as vias to connect metal layers which are separated by a dielectric layer. Such contact vias are formed on either side of a sacrificial metallization area, and then the interconnect metallization is removed from between the contact vias, leaving them separated. Dielectric surrounding the contacts is etched back so that they protrude toward each other. Thus, when the contacts are moved toward each other by actuating the MEM switch, they connect firmly without obstruction.

US Patent:

6535443, Mar 18, 2003

Filed:

Jun 13, 2002

Appl. No.:

10/171907

Inventors:

Paul H. OuYang - San Jose CA
Donald Liusie - San Jose CA

Assignee:

DMEL Incorporated - Santa Clara CA

International Classification:

G11C 700

US Classification:

365207, 365204, 365208

Abstract:

The rate of discharge of the sense amplifier and bit lines in a memory circuit is controlled to simulate a boosted sense ground potential without requiring the use of a voltage regulator or precharged capacitors. The sense amplifier is electrically coupled to ground through a large transistor during a first period, which quickly discharges the sense amplifier toward ground potential to ensure a fast sense speed of the sense amplifier. During a subsequent period, the large transistor is turned off and the sense amplifier is electrically coupled to ground through a smaller transistor. The small transistor slowly discharges the sense amplifier towards ground, without reaching ground, until the active cycle is over and the discharge of the sense amplifier is terminated. By holding the sense amplifier above, but near, ground potential, the subthreshold leakage of non-selected memory cells is minimized so that the frequency of refresh may be decreased, thereby minimizing standby current.

US Patent:

6667245, Dec 23, 2003

Filed:

Dec 13, 2001

Appl. No.:

10/016894

Inventors:

Tsung-Yuan Hsu - Westlake Village CA
Daniel J. Hyman - Cleveland OH
Robert Y. Loo - Agoura Hills CA
Paul Ouyang - San Jose CA
James H. Schaffner - Chatsworth CA
Adele Schmitz - Newbury Park CA
Robert N. Schwartz - Costa Mesa CA

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01L 2100

US Classification:

438723, 216 2, 216 79, 438739, 438740, 438743

Abstract:

A microelectromechanical (MEM) switch is fabricated inexpensively by using processing steps which are standard for fabricating multiple metal layer integrated circuits, such as CMOS. The exact steps may be adjusted to be compatible with the process of a particular foundry, resulting in a device which is both low cost and readily integrable with other circuits. The processing steps include making contacts for the MEM switch from metal plugs which are ordinarily used as vias to connect metal layers which are separated by a dielectric layer. Such contact vias are formed on either side of a sacrificial metallization area, and then the interconnect metallization is removed from between the contact vias, leaving them separated. Dielectric surrounding the contacts is etched back so that they protrude toward each other. Thus, when the contacts are moved toward each other by actuating the MEM switch, they connect firmly without obstruction.

US Patent:

8111089, Feb 7, 2012

Filed:

May 24, 2010

Appl. No.:

12/786205

Inventors:

Ronald P. Cocchi - Seal Beach CA, US
James P. Baukus - Westlake Village CA, US
Bryan J. Wang - S. Lake Tahoe CA, US
Lap Wai Chow - S. Pasadena CA, US
Paul Ouyang - San Jose CA, US

Assignee:

Syphermedia International, Inc. - Westminster CA
Promtek Programmable Memory Technology, Inc. - San Jose CA

International Classification:

H03K 19/00
H03K 19/20
H03K 19/094

US Classification:

326121, 326113, 326 8

Abstract:

A logical building block and method of using the building block to design a logic cell library for CMOS (Complementary Metal Oxide Silicon) ASICs (Application Specific Integrated Circuits) is disclosed. Different logic gates, built with the same building block as described in this invention, will have the same schematics of transistor connection and also the same physical layout so that they appear to be physically identical under optical or electron microscopy. An ASIC designed from a library of such logic cells is strongly resistant to a reverse engineering attempt.

US Patent:

8168487, May 1, 2012

Filed:

Sep 13, 2007

Appl. No.:

11/855005

Inventors:

Lap Wai Chow - South Pasadena CA, US
Gavin Harbison - Marina del Rey CA, US
Paul Ouyang - San Jose CA, US

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01L 21/335

US Classification:

438183, 257E21438, 257E29266

Abstract:

A technique for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor substrate, at least some of the transistors being of the type having sidewall spacers with LDD regions formed under the sidewall spacers. Transistors are programmably interconnected with ambiguous interconnection features, the ambiguous interconnection features each comprising a channel formed in the semiconductor substrate with preferably the same dopant density as the LDD regions, with selected ones of the channels being formed of a conductivity type supporting electrical communication between interconnected active regions and with other selected ones of the channels being formed of a conductivity type inhibiting electrical communication but ambiguously appearing to a reverse engineer as supporting electrical communication.

US Patent:

8564073, Oct 22, 2013

Filed:

Mar 16, 2012

Appl. No.:

13/423155

Inventors:

Lap Wai Chow - South Pasadena CA, US
Gavin Harbison - Marina del Rey CA, US
Paul Ouyang - San Jose CA, US

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01L 29/66

US Classification:

257408, 257E29266

Abstract:

A technique for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor substrate, at least some of the transistors being of the type having sidewall spacers with LDD regions formed under the sidewall spacers. Transistors are programmably interconnected with ambiguous interconnection features, the ambiguous interconnection features each comprising a channel formed in the semiconductor substrate with preferably the same dopant density as the LDD regions, with selected ones of the channels being formed of a conductivity type supporting electrical communication between interconnected active regions and with other selected ones of the channels being formed of a conductivity type inhibiting electrical communication but ambiguously appearing to a reverse engineer as supporting electrical communication.