Paul D Berndt

US Patent:

6825683, Nov 30, 2004

Filed:

Apr 18, 2002

Appl. No.:

10/125117

Inventors:

Paul D. Berndt - Woodinville WA
Jarie G. Bolander - Redwood City CA
Leah S. Clark - San Diego CA

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G10R 3102

US Classification:

324763, 324765

Abstract:

In one embodiment, a test circuit is coupled to receive a first signal from a signal generator such as a test equipment. The test circuit allows access to one or more terminals of a first integrated circuit, a second integrated circuit, or both based at least on the signal. The test circuit may be in the first integrated circuit. The first integrated circuit and the second integrated circuit may be in a single package. In one embodiment, the test circuit routes signals to and from the second integrated circuit, thus allowing the second integrated circuit to be tested as if it was stand-alone. In one embodiment, the test circuit allows access to otherwise inaccessible terminals of the first integrated circuit, the second integrated circuit, or both.

US Patent:

7428678, Sep 23, 2008

Filed:

Aug 30, 2005

Appl. No.:

11/215278

Inventors:

Paul D. Berndt - Woodinville WA, US
Steven Larky - Del Mar CA, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G01R 31/28

US Classification:

714729, 714727

Abstract:

In one embodiment, an integrated circuit includes a serial link interface configured to send and receive data over a serial bus both during normal operation and during scan tests. The integrated circuit may include data routing circuitry for transferring data between the serial link interface and a scan chain during a scan test, and for transferring data between the serial link interface and a core logic circuit of the integrated circuit, without going through the scan chain, during normal operation. Scan data may be generated and analyzed by a tester integrated circuit coupled to the integrated circuit over the serial bus.

US Patent:

63208113, Nov 20, 2001

Filed:

Dec 10, 1998

Appl. No.:

9/208889

Inventors:

Warren A. Snyder - Snohomish WA
Paul D. Berndt - Woodinville WA

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G11C 800

US Classification:

36523003

Abstract:

A circuit comprising a memory array having a first region, a second region, a plurality of bitlines and an X-decoder. A plurality of transistors may each coupled between the first and second regions, where each of the transistors may be configured to (i) separate the first and the second region during a read operation and (ii) join the first and the second region during a write operation. Alternatively, a plurality of memory regions may be implemented, each separated by another plurality of transistors.

US Patent:

20220344563, Oct 27, 2022

Filed:

Apr 27, 2021

Appl. No.:

17/241688

Inventors:

- Redmond WA, US
Adam James MUFF - Woodinville WA, US
Indranil SEN - Bellevue WA, US
Paul D BERNDT - Shoreline WA, US

International Classification:

H01L 39/10
G06N 10/00

Abstract:

Embodiments of the present disclosure include techniques for interfacing with superconducting circuits and systems. In one embodiment, the present disclosure includes interface circuitry, including driver circuits and/or receiver circuits to send/receive signals with a superconducting circuit. In another embodiment, the present disclosure includes superconducting circuits and techniques for generating a trigger signal from and external clock that is based on a superconducting resonator. In yet another embodiment, the present disclosure includes superconducting data capture circuits that may be used to couple external data to and/or from superconducting logic.