Orb O Acton

US Patent:

20220246608, Aug 4, 2022

Filed:

Apr 21, 2022

Appl. No.:

17/726412

Inventors:

- Santa Clara CA, US
Anh PHAN - Beaverton OR, US
Ehren MANNEBACH - Tigard OR, US
Cheng-Ying HUANG - kPortland OR, US
Stephanie A. BOJARSKI - Beaverton OR, US
Gilbert DEWEY - Beaverton OR, US
Orb ACTON - Portland OR, US
Willy RACHMADY - Beaverton OR, US

International Classification:

H01L 27/088
H01L 29/423
H01L 29/08
H01L 21/762
H01L 23/528
H01L 29/78
H01L 29/06

Abstract:

Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.

US Patent:

20220199472, Jun 23, 2022

Filed:

Dec 23, 2020

Appl. No.:

17/132995

Inventors:

- Santa Clara CA, US
Bishwajeet Guha - Hillsboro OR, US
Brian Greene - Portland OR, US
Chung-Hsun Lin - Portland OR, US
Curtis Tsai - , US
Orb Acton - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/8234
H01L 27/088
H01L 27/12
H01L 21/84

Abstract:

Integrated circuitry comprising high voltage (HV) and low voltage (LV) ribbon or wire (RoW) transistor stack structures. In some examples, a gate electrode of the HV and LV transistor stack structures may include the same work function metal. A metal oxide may be deposited around one or more channels of the HV transistor stack, thereby altering the dipole properties of the gate insulator stack from those of the LV transistor stack structure.

US Patent:

20230090092, Mar 23, 2023

Filed:

Sep 22, 2021

Appl. No.:

17/448382

Inventors:

Aaron D. Lilak - Beaverton OR, US
Orb Acton - Portland OR, US
Cheng-Ying Huang - Hillsboro OR, US
Gilbert Dewey - Beaverton OR, US
Ehren Mannebach - Tigard OR, US
Anh Phan - Beaverton OR, US
Willy Rachmady - Beaverton OR, US
Jack T. Kavalieros - Portland OR, US

International Classification:

H01L 27/12
H01L 21/84

Abstract:

An integrated circuit having a transistor architecture includes a first semiconductor body and a second semiconductor body. The first and second semiconductor bodies are arranged vertically (e.g., stacked configuration) or horizontally (e.g., forksheet configuration) with respect to each other, and separated from one another by insulator material, and each can be configured for planar or non-planar transistor topology. A first gate structure is on the first semiconductor body, and includes a first gate electrode and a first high-k gate dielectric. A second gate structure is on the second semiconductor body, and includes a second gate electrode and a second high-k gate dielectric. In an example, the first gate electrode includes a layer comprising a compound of silicon and one or more metals; the second gate structure may include a silicide workfunction layer, or not. In one example, the first gate electrode is n-type, and the second gate electrode is p-type.

US Patent:

20200006330, Jan 2, 2020

Filed:

Jun 29, 2018

Appl. No.:

16/024076

Inventors:

- Santa Clara CA, US
ANH PHAN - Beaverton OR, US
EHREN MANNEBACH - Beaverton OR, US
CHENG-YING HUANG - Hillsboro OR, US
STEPHANIE A. BOJARSKI - Beaverton OR, US
GILBERT DEWEY - Beaverton OR, US
ORB ACTON - Portland OR, US
WILLY RACHMADY - Beaverton OR, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

H01L 27/088
H01L 29/423
H01L 29/08
H01L 29/06
H01L 23/528
H01L 29/78
H01L 21/762

Abstract:

Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.