Navneeth L Kankani

US Patent:

20170309344, Oct 26, 2017

Filed:

Jul 2, 2017

Appl. No.:

15/640563

Inventors:

- Plano TX, US
Arash Hazeghi - Emeryville CA, US
Cynthia Hsu - Milpitas CA, US
Navneeth Kankani - Fremont CA, US

Assignee:

SANDISK TECHNOLOGIES LLC - Plano TX

International Classification:

G11C 16/34
G11C 16/32
G11C 16/04

Abstract:

Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.

US Patent:

20150347039, Dec 3, 2015

Filed:

Jul 1, 2014

Appl. No.:

14/321701

Inventors:

- Milpitas CA, US
Allen Samuels - San Jose CA, US
Navneeth Kankani - Fremont CA, US

International Classification:

G06F 3/06

Abstract:

A storage system includes a memory controller and a storage device with one or more memory devices, each with a plurality of memory portions. The memory controller determines an initial storage capacity for each of the one or more memory devices, where the one or more memory devices are configured in a first storage density. The memory controller detects a trigger condition as to at least one memory portion of a respective device of the one or more memory devices and, in response to detecting the trigger condition, recharacterizes the at least one memory portion of the respective memory device so as to be configured in a second storage density, where the at least one recharacterized memory portion of the respective memory device has a reduced storage capacity. After the recharacterizing, the memory controller determines a revised storage capacity for the respective memory device.

US Patent:

20150347229, Dec 3, 2015

Filed:

Nov 17, 2014

Appl. No.:

14/543813

Inventors:

- Plano TX, US
Robert W. Ellis - Phoenix AZ, US
Neil R. Darragh - Edinburgh, GB
Aaron K. Olbrich - Morgan Hill CA, US
Navneeth Kankani - Fremont CA, US
Steven Sprouse - San Jose CA, US

International Classification:

G06F 11/10
G11C 29/52

Abstract:

A memory controller configures a plurality of word lines associated with a respective block of a 3D memory device in a first configuration, where the first configuration includes a set of configuration parameters for each word line of the plurality of word lines determined at least in part on the vertical positions of each word line relative to a substrate of the 3D memory device and, while the plurality of word lines are configured in the first configuration, writes data to and reads data from the respective block. For the respective block, the memory controller: adjusts a first parameter in the respective set of configuration parameters corresponding to a respective word line of the plurality of word lines in response to detecting a first trigger condition as to the respective word line and, after adjusting the first parameter, writes data to and reads data from the respective word line.