Morris Marden from 2226 Thorncroft Dr, Beaverton, OR 97124, age 47, Phone: 5035337582

Isbn (Books And Publications)

Geometry Of Polynomials
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Author:

Morris Marden
ISBN #:

0821815032

Us Patents

Decoupling The Number Of Logical Threads From The Number Of Simultaneous Physical Threads In A Processor
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US Patent:

7797683, Sep 14, 2010
Filed:

Dec 29, 2003
Appl. No.:

10/745527
Inventors:

Per H. Hammarlund - Hillsboro OR, US
Stephan J. Jourdan - Portland OR, US
Pierre Michaud - Bruz, FR
Alexandre J. Farcy - Hillsboro OR, US
Morris Marden - Hillsboro OR, US
Robert L. Hinton - Hillsboro OR, US
Douglas M. Carmean - Beaverton OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 9/44
US Classification:

717127
Abstract:

Systems and methods of managing threads provide for supporting a plurality of logical threads with a plurality of simultaneous physical threads in which the number of logical threads may be greater than or less than the number of physical threads. In one approach, each of the plurality of logical threads is maintained in one of a wait state, an active state, a drain state, and a stall state. A state machine and hardware sequencer can be used to transition the logical threads between states based on triggering events and whether or not an interruptible point has been encountered in the logical threads. The logical threads are scheduled on the physical threads to meet, for example, priority, performance or fairness goals. It is also possible to specify the resources that are available to each logical thread in order to meet these and other, goals. In one example, a single logical thread can speculatively use more than one physical thread, pending a selection of which physical thread should be committed.

Providing Quality Of Service Via Thread Priority In A Hyper-Threaded Microprocessor
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US Patent:

8095932, Jan 10, 2012
Filed:

Aug 14, 2007
Appl. No.:

11/838458
Inventors:

Matthew Merten - Hillsboro OR, US
Santhosh Srinath - Kirkland WA, US
Morris Marden - Hillsboro OR, US
John Holm - Beaverton OR, US
Glenn Hinton - Portland OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 9/46
US Classification:

718104, 718103
Abstract:

A method and apparatus for providing quality of service in a multi-processing element environment based on priority is herein described. Consumption of resources, such as a reservation station and a pipeline, are biased towards a higher priority processing element. In a reservation station, mask elements are set to provide access for higher priority processing elements to more reservation entries. In a pipeline, bias logic provides a ratio of preference for selection of a high priority processing element for further processing in the pipeline.

Providing Thread Fairness By Biasing Selection Away From A Stalling Thread Using A Stall-Cycle Counter In A Hyper-Threaded Microprocessor
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US Patent:

8438369, May 7, 2013
Filed:

Nov 8, 2010
Appl. No.:

12/941615
Inventors:

Morris Marden - Hillsboro OR, US
Matthew Merten - Hillsboro OR, US
Alexandre Farcy - Hillsboro OR, US
Avinash Sodani - Portland OR, US
James Hadley - Portland OR, US
Ilhyun Kim - Beaverton OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 9/40
US Classification:

712220
Abstract:

A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline.

Providing Thread Fairness By Biasing Selection Away From A Stalling Thread Using A Stall-Cycle Counter In A Hyper-Threaded Microprocessor
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US Patent:

8521993, Aug 27, 2013
Filed:

Apr 9, 2007
Appl. No.:

11/784864
Inventors:

Morris Marden - Hillsboro OR, US
Matthew Merten - Hillsboro OR, US
Alexandre Farcy - Hillsboro OR, US
Avinash Sodani - Portland OR, US
James Hadley - Portland OR, US
Ilhyun Kim - Beaverton OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 9/40
US Classification:

712220
Abstract:

A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline.

Detecting And Resolving Locks In A Memory Unit
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US Patent:

20080059723, Mar 6, 2008
Filed:

Aug 31, 2006
Appl. No.:

11/513636
Inventors:

Prakash Math - Hillsboro OR, US
Matthew Merten - Hillsboro OR, US
Sebastien Hily - Hillsboro OR, US
Beeman Strong - Portland OR, US
Morris Marden - Hillsboro OR, US
David Burns - Portland OR, US
International Classification:

G06F 13/00
US Classification:

711154
Abstract:

In one embodiment, the present invention includes an apparatus having a first counter to count dispatches of a senior request in a memory unit, a second counter to count cycles of a processor coupled to the memory unit, and a controller coupled to the first and second counters to execute one or more one remediation measures with respect to the senior request based on a value of at least one of the counters. Other embodiments are described and claimed.

Providing Thread Fairness In A Hyper-Threaded Microprocessor
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US Patent:

20110055524, Mar 3, 2011
Filed:

Nov 8, 2010
Appl. No.:

12/941637
Inventors:

Morris Marden - Hillsboro OR, US
Matthew Merten - Hillsboro OR, US
Alexandre Farcy - Hillsboro OR, US
Avinash Sodani - Portland OR, US
James Hadley - Portland OR, US
Ilhyun Kim - Beaverton OR, US
International Classification:

G06F 9/30
US Classification:

712217, 712E09032, 712E09023
Abstract:

A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline.

Processor With Second Jump Execution Unit For Branch Misprediction
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US Patent:

20140195790, Jul 10, 2014
Filed:

Dec 28, 2011
Appl. No.:

13/994676
Inventors:

Matthew C. Merten - Hillsboro OR, US
Avinash Sodani - Portland OR, US
Sean P. Mirkes - Beaverton OR, US
Vijaykumar B. Kadgi - Portland OR, US
Bambang Sutanto - Portland OR, US
Chia Yin Kevin Lai - Portland OR, US
Morris Marden - Hillsboro OR, US
Alexandre J. Farcy - Hillsboro OR, US
International Classification:

G06F 9/38
US Classification:

712239
Abstract:

A secondary jump execution unit (JEU) is incorporated in a micro-processor to operate concurrently with a primary JEU, enabling the execution of simultaneous branch operations with possible detection of multiple branch mispredicts. When branch operations are executed on both JEUs in a same instruction cycle, mispredict processing for the secondary JEU is skidded into the primary JEU's dispatch pipeline such that the branch processing for the secondary JEU occurs after processing of the branch for the primary JEU and while the primary JEU is not processing a branch. Moreover, in cases when a nuke command is also received from a reorder buffer of the processor, the branch processing for the secondary JEU is further delayed to accommodate processing of the nuke on the primary JEU. Further embodiments support the promotion of the secondary JEU to have access to the mispredict mechanisms of the primary JEU in certain circumstances.

Memory Renaming Mechanism In Microarchitecture
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US Patent:

20140095814, Apr 3, 2014
Filed:

Sep 28, 2012
Appl. No.:

13/631644
Inventors:

MORRIS MARDEN - Hillsboro OR, US
VIJAYKUMAR VIJAY KADGI - Portland OK, US
JAMES D. HADLEY - Portland OR, US
MATTHEW C. MERTEN - Hillsboro OR, US
GRACE C. LEE - Portland OR, US
JOSEPH A. MCMAHON - Portland OR, US
ROBERT S. CHAPPELL - Portland OR, US
LAURA A. KNAUTH - Portland OR, US
FARIBORZ TABESH - Portland OR, US
International Classification:

G06F 12/00
US Classification:

711156, 711E12001
Abstract:

A processor includes a processing unit including a storage module having stored thereon a table for tracking physical registers in which each store operation stores source data and a memory renaming module for register renaming load operations based on the table.