Moiz Badrudin Khambaty

US Patent:

20130234198, Sep 12, 2013

Filed:

Mar 6, 2012

Appl. No.:

13/413621

Inventors:

Moiz Khambaty - Santa Clara CA, US
David Burgess - Santa Clara CA, US
Vallangiman V. Srinivasan - San Francisco CA, US

Assignee:

Manufacturing Networks Incorporated (MNI) - Santa Clara CA

International Classification:

H01L 29/88
H01L 29/861

US Classification:

257106, 257508, 257E29339, 257E29328

Abstract:

A novel electrical circuit protection design with dielectrically-isolated diode configuration and architecture is disclosed. In one embodiment of the invention, a plurality of diodes connected in series is monolithically integrated in a single piece of semiconductor substrates by utilizing dielectrically-isolated trenching and silicon-on-insulator substrates, which enable formation of “silicon islands” to insulate a diode structure electrically from adjacent structures. In one embodiment of the invention, the plurality of diodes connected in series includes at least one Zener diode, which provides a clamping voltage approximately equal to its breakdown voltage value in case of a voltage spike or a power surge event. In another embodiment of the invention, the plurality of diodes connected in series includes a scalable number of monolithically-integrated forward-bias PN diodes, wherein the summation of the forward-bias voltage of each PN diode is equivalent to a net clamping voltage value for an electrical circuit protection design.

US Patent:

54932513, Feb 20, 1996

Filed:

Dec 2, 1994

Appl. No.:

8/349503

Inventors:

Moiz Khambaty - Sunnyvale CA
Corey D. Petersen - Pleasanton CA

Assignee:

IMP, Inc. - San Jose CA

International Classification:

H01L 2500

US Classification:

327564

Abstract:

A method of threshold adjust implantation which involves the implanting of some of the PMOS FETs' channels on a CMOS circuit so the PMOS FETs have a threshold voltage of substantially zero volts, the implanting involves an additional implantation of ions into the PMOS FET' channels in addition to the implantation required to raise the PMOS FET' threshold voltage from the native threshold voltage to the normal threshold voltage.

US Patent:

54078490, Apr 18, 1995

Filed:

Jun 23, 1992

Appl. No.:

7/902914

Inventors:

Moiz Khambaty - Sunnyvale CA
Corey D. Petersen - Pleasanton CA

Assignee:

IMP, Inc. - San Jose CA

International Classification:

H01L 21266

US Classification:

437 45

Abstract:

A method of threshold adjust implantation which involves the implanting of some of the PMOS FETs' channels on a CMOS circuit so the PMOS FETs have a threshold voltage of substantially zero volts, the implanting involves an additional implantation of ions into the PMOS FETs' channels in addition to the implantation required to raise the PMOS FETs' threshold voltage from the native threshold voltage to the normal threshold voltage.