Michael J Tooher

US Patent:

6977860, Dec 20, 2005

Filed:

May 22, 2004

Appl. No.:

10/851767

Inventors:

Michael J. Tooher - Mountain View CA, US
John M. Callahan - San Ramon CA, US

Assignee:

Virtual Silicon Technology, Inc. - Sunnyvale CA

International Classification:

G11C008/00

US Classification:

36523003, 365188, 36523002, 365227

Abstract:

A SRAM uses a number of memory banks in a configuration that uses lower voltage swings on a differential internal data bus so that the internal data bus no longer uses single-ended VDD/VSS, HIGH-to-LOW, rail-to-rail voltage swing for a read mode of operation. This consumes less power for a read operation. Senseamps for finally converting low-level signals to full logic output voltage levels are located right next to output buffers and data output pads for the SRAM. The bit lines for a memory CORE are formed in lower metal layers that are closer to the core memory cells and, thus, have higher capacitance. The present invention uses lower-capacitance top layers 4–6 of a 6 metal layer scheme for the signal lines of the differential internal data bus. An optimum configuration has the capacitance of a bitline equal to the capacitance of the differential internal data bus bit-line.

US Patent:

7046561, May 16, 2006

Filed:

Apr 16, 2003

Appl. No.:

10/417791

Inventors:

Michael Tooher - Mountain View CA, US

International Classification:

G11C 7/00

US Classification:

365201, 365200

Abstract:

An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance from a variety of sources. A control block is located on the ASIC chip outside of the memory instances. The control block has a defective memory register for storing an address of a defective memory subunit. The address of a defective memory subunit from the defective memory register in the control block is transferred to the universal interface register in the memory instance. In one embodiment, the control block includes fuses for storing a defective subunit address in binary form. A fuse array is located outside of the memory instances and contains laser fuses that represent address of defective subunits for each memory instance. Alternatively, the control block includes a BISTDR (built-in, self-test, diagnostic, and repair) system that provides an address of a defective memory subunit.

US Patent:

7154792, Dec 26, 2006

Filed:

May 8, 2006

Appl. No.:

11/430393

Inventors:

Michael Tooher - Mountain View CA, US

International Classification:

G11C 7/00

US Classification:

365200, 365201

Abstract:

An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance from a variety of sources. A control block is located on the ASIC chip outside of the memory instances. The control block has a defective memory register for storing an address of a defective memory subunit. The address of a defective memory subunit from the defective memory register in the control block is transferred to the universal interface register in the memory instance. In one embodiment, the control block includes fuses for storing a defective subunit address in binary form. A fuse array is located outside of the memory instances and contains laser fuses that represent address of defective subunits for each memory instance. Alternatively, the control block includes a BISTDR (built-in, self-test, diagnostic, and repair) system that provides an address of a defective memory subunit.

US Patent:

7460413, Dec 2, 2008

Filed:

Aug 31, 2006

Appl. No.:

11/468898

Inventors:

Michael Tooher - Mountain View CA, US

International Classification:

G11C 7/06

US Classification:

36518907, 365200, 365201, 3652257

Abstract:

An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance from a variety of sources. A control block is located on the ASIC chip outside of the memory instances. The control block has a defective memory register for storing an address of a defective memory subunit. The address of a defective memory subunit from the defective memory register in the control block is transferred to the universal interface register in the memory instance. In one embodiment, the control block includes fuses for storing a defective subunit address in binary form. A fuse array is located outside of the memory instances and contains laser fuses that represent address of defective subunits for each memory instance. Alternatively, the control block includes a BISTDR (built-in, self-test, diagnostic, and repair) system that provides an address of a defective memory subunit.

US Patent:

7675809, Mar 9, 2010

Filed:

Nov 11, 2008

Appl. No.:

12/268968

Inventors:

Michael J. Tooher - Mountain View CA, US

International Classification:

G11C 7/06

US Classification:

36523008, 365200, 365201, 3652257

Abstract:

An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance from a variety of sources. A control block is located on the ASIC chip outside of the memory instances. The control block has a defective memory register for storing an address of a defective memory subunit. The address of a defective memory subunit from the defective memory register in the control block is transferred to the universal interface register in the memory instance. In one embodiment, the control block includes fuses for storing a defective subunit address in binary form. A fuse array is located outside of the memory instances and contains laser fuses that represent address of defective subunits for each memory instance. Alternatively, the control block includes a BISTDR (built-in, self-test, diagnostic, and repair) system that provides an address of a defective memory subunit.

US Patent:

7684262, Mar 23, 2010

Filed:

Apr 27, 2007

Appl. No.:

11/741647

Inventors:

Michael Anthony Zampaglione - San Jose CA, US
Michael Tooher - Mountain View CA, US

Assignee:

Mosaid Technologies Incorporated - Ottawa

International Classification:

G11C 5/14

US Classification:

36518909, 365154, 36521012

Abstract:

A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of V−(1. 5*V), or maintain 1. 5*Vacross the memory cells, where Vis a threshold voltage of an SRAM memory cell transistor and Vis a positive supply voltage. By tracking the Vof the memory cell transistors in the SRAM array, the circuit reduces leakage current while maintaining data integrity. A threshold voltage reference circuit can include one or more memory cell transistors (in parallel), or a specially wired memory cell to track the memory cell transistor threshold voltage. The value of the virtual ground reference voltage can be based on a ratio of feedback chain elements in a multiplier circuit.

US Patent:

7760575, Jul 20, 2010

Filed:

Dec 31, 2007

Appl. No.:

11/968021

Inventors:

Michael James Tooher - Mountain View CA, US
Prakash Ravikumar Bhatia - Fremont CA, US

Assignee:

Virage Logic Corp. - Fremont CA

International Classification:

G11C 5/14

US Classification:

365226, 365154, 36523003

Abstract:

In one embodiment, a static random access memory (SRAM) is operable with first voltage and second voltages and includes a plurality of SRAM cells arranged in rows and columns, each SRAM cell being coupled to a respective wordline, respective complementary bitlines, and a source line and a control circuit connected between the source line and the second voltage. The control circuit is selectively operable in a working mode in which data in the plurality of SRAM cells can be accessed, a sleep mode is which data is retained but leakage is reduced and a shutdown mode in which the source line is allowed to float to a level that is substantially equal to the first voltage.

US Patent:

7990787, Aug 2, 2011

Filed:

Feb 5, 2010

Appl. No.:

12/701519

Inventors:

Michael J. Tooher - Mountain View CA, US

Assignee:

Stellar Kinetics, LLC - Las Vegas NV

International Classification:

G11C 29/00

US Classification:

365200, 36518907

Abstract:

An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance from a variety of sources. A control block is located on the ASIC chip outside of the memory instances. The control block has a defective memory register for storing an address of a defective memory subunit. The address of a defective memory subunit from the defective memory register in the control block is transferred to the universal interface register in the memory instance. In one embodiment, the control block includes fuses for storing a defective subunit address in binary form. A fuse array is located outside of the memory instances and contains laser fuses that represent address of defective subunits for each memory instance. Alternatively, the control block includes a BISTDR (built-in, self-test, diagnostic, and repair) system that provides an address of a defective memory subunit.