Michael Irving Mandell

US Patent:

6374204, Apr 16, 2002

Filed:

Feb 18, 1998

Appl. No.:

09/025762

Inventors:

Michael I. Mandell - Los Angeles CA
Arnold L. Berman - Los Angeles CA
Wei-Chun Wang - Temple City CA

Assignee:

Hughes Electronics Corporation - El Segundo CA

International Classification:

G06F 1750

US Classification:

703 14, 703 18, 703 2

Abstract:

A unique transistor model and methods for analyzing the model are disclosed. The transistor model of the present invention is simple and requires specification of a minimal number of parameters to simulate transistor operation. Three analysis methods are disclosed, each having unique circumstances for application A first method is premised on sampling all waveforms in the circuit and determining the operating point of the transistor. The first method assumes an input of an arbitrary periodic waveform. The first method is very flexible and may be used with a wide range of models other than the disclosed model. A second and a third method are premised on input and output waveform clipping. The second method assumes a single tone input into the transistor. The third method is a combination of features from the first and second methods. The third method is computationally efficient and assumes an arbitrary periodic input waveform.

US Patent:

6477689, Nov 5, 2002

Filed:

Jun 13, 2001

Appl. No.:

09/880444

Inventors:

Michael I Mandell - Los Angeles CA
Arnold L. Berman - Los Angeles CA

Assignee:

The Boeing Company - Chicago IL

International Classification:

G06F 1750

US Classification:

716 11, 716 18

Abstract:

A computer-implemented design tool architecture provides a mechanism for characterizing a circuit at a hardware level. The tool architecture has a medium for storing a description of an application specific integrated circuit (ASIC), where the description describes the ASIC at a behavioral level of a hierarchy. A library of foundry primitives map known ASIC components to code sets for a hardware description language (HDL). The tool architecture further includes a command interpreter for generating an electronic file based on a set of predefined computer-based commands such that the electronic file characterizes the circuit at the hardware level. The hardware level is at a lower level in the hierarchy than the behavioral level.

US Patent:

6757884, Jun 29, 2004

Filed:

Jul 31, 2001

Appl. No.:

09/918596

Inventors:

Michael I. Mandell - Los Angeles CA
Arnold L. Berman - Los Angeles CA

Assignee:

The Boeing Company - Chicago IL

International Classification:

G06F 1750

US Classification:

716 18

Abstract:

A design tool and method for characterizing a circuit at a hardware level includes the steps of generating a behavioral level description of the circuit and generating a netlist from the behavioral level description. Reference equations are generated from the netlist and are translated into numeric and symbolic C-code. The symbolic C-code is compared to the numeric C-code for validation. The reference equations are translated into numeric and symbolic HDL-code. The symbolic HDL-code is compared to the numeric HDL-code for validation. The symbolic C-code is compiled and simulated. A C-code equation file is generated. The symbolic HDL-code is compiled and simulated. A HDL-code equation file is generated. A symbolic manipulation program is used to solve for a difference between the C-code equation file and the HDL-code equation file. If there are no unexpected differences, equivalence is established.

US Patent:

6940896, Sep 6, 2005

Filed:

Mar 26, 2001

Appl. No.:

09/817402

Inventors:

Michael I. Mandell - Los Angeles CA, US
Arnold L. Berman - Los Angeles CA, US

Assignee:

The Boeing Company - Chicago IL

International Classification:

H04B001/10

US Classification:

375150, 375350, 375229, 708300, 708301

Abstract:

An improved method is provided for seamlessly combining adjacent subchannels in a signal processing system. Each adjacent subchannel is defined to include a first and a second linear phase digital filter, where the filters are implemented using digital circuitry having a plurality of registers. Prior to summing the two adjacent channels, a delay is introduced into one of the two filters in each of the subchannels, such that the delay is equal to the delay associated with one register in the digital circuitry. The two adjacent subchannels are then combined to form a composite channel that exhibits linear phase.

US Patent:

7006961, Feb 28, 2006

Filed:

Aug 13, 2001

Appl. No.:

09/928848

Inventors:

Michael I. Mandell - Los Angeles CA, US
Arnold L. Berman - Los Angeles CA, US

Assignee:

The Boeing Company - Chicago IL

International Classification:

G06F 17/50

US Classification:

703 15, 703 13, 703 14, 703 19, 716 7, 716 18

Abstract:

A design tool and method characterizes a circuit at a hardware level description. A behavioral level description of the circuit is created. Symbolic equations for components of the behavioral level description are created. The behavioral level description is partitioned by inserting a marker component into the behavioral level description of the circuit to simplify subsequent processing used to prove equivalence between the behavioral and hardware level descriptions. The symbolic equations are back-substituted until output variables are expressed in terms of input variables that determine the output variables. The marker component is defined using a unique symbolic name. Current time counts of each clock cycle are used to compute an index for the marker component. The behavioral level description is transformed to produce symbolic and numeric files for compilation to gates and proof of functionality.

US Patent:

20030144826, Jul 31, 2003

Filed:

Jan 29, 2002

Appl. No.:

10/059751

Inventors:

Michael Mandell - Los Angeles CA, US
Timothy Koehler - Redondo Beach CA, US
Arnold Berman - Los Angeles CA, US

International Classification:

G06F017/50

US Classification:

703/014000

Abstract:

A method and computer system formally verifies a synthesis of integrated circuit designs that include pipeline registers. A hardware description language (HDL) representation of an integrated circuit is parsed. Components and connections of the HDL representation are identified. Pipeline register components of the HDL representation are removed. The removed pipeline register components are replaced with a conductor. Pipeline register components are added between output logic gates and output registers of the HDL representation to create a new HDL representation. Formal verification of the new HDL representation is performed using a verification tool.

US Patent:

59559179, Sep 21, 1999

Filed:

Aug 27, 1997

Appl. No.:

8/921749

Inventors:

Michael I. Mandell - Los Angeles CA
Chak M. Chie - Culver City CA
Wei-Chun Wang - Temple City CA
Arnold L. Berman - Los Angeles CA

Assignee:

Hughes Electronics Corporation - El Segundo CA

International Classification:

G01R 1900
H03F 366
H03G 320

US Classification:

330 2

Abstract:

Apparatus and methods that compensate for the effects of gain and phase variations of a high power amplifier in the presence of multicarrier traffic. The calibration system and method impose negligible degradation to the multicarrier traffic processed by the high power amplifier. A calibration signal generator is used to generate a plurality of nondisrupting calibration signals, such as pseudorandom numbers, which are also summed and combined with the multicarrier traffic signals. The plurality of nondisrupting calibration signals are also combined to produce a combined nondisrupting calibration signal. Each of the nondisrupting calibration signals is selectively output and is combined with sampled versions of the amplified multicarrier traffic signals produced by the high power amplifier to despread them. The despread multicarrier traffic signals are then processed in a processor to generate signals indicative of total signal power, intermodulation power, and phase shift of the despread multicarrier traffic signals to determine a current operating point of the high power amplifier on its gain transfer curve. Gain and phase control signals are generated by a processor that are coupled to the gain control and phase control circuits to set the amplifier at its most desirable operating point.

US Patent:

60773030, Jun 20, 2000

Filed:

Apr 28, 1998

Appl. No.:

9/067216

Inventors:

Michael I. Mandell - Los Angeles CA
Arnold L. Berman - Los Angeles CA
Wei-Chun Wang - Temple City CA

Assignee:

Hughes Electronics Corporation - El Segundo CA

International Classification:

G06F 1750

US Classification:

703 14

Abstract:

An algorithm (20) or method (20) for verifying that a system hierarchically built from smaller components implements a desired equation that represents the system. Symbolic data is clocked (24) through the system by processing a symbolic test vector using linked equations (22) written (21) for each component of the system. A resulting symbolic equation generated at the output of the system is recorded (25). The symbolic equation is then compared (26) with the desired equation for the system using a symbolic manipulation tool. If the comparison generates a zero difference, the system correctly implements the desired equation representative of the system, and vice-versa.

Author:

Michael A. Mandell

ISBN #:

0821838148