Michael J Garland

US Patent:

8065288, Nov 22, 2011

Filed:

Nov 9, 2007

Appl. No.:

11/938091

Inventors:

Michael J. Garland - Lake Elmo MN, US
Samuli M. Laine - Vantaa, FI
Timo O. Aila - Tuusula, FI

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 7/00
G06F 17/30

US Classification:

707706, 345419

Abstract:

A system, method, and computer program product are provided for testing a query against multiple sets of objects. In operation, a query is tested against a first set of objects, utilizing a single instruction multiple data processing architecture. Additionally, a second set of objects is selected based on a result of testing the query against the first set of objects. Furthermore, the query is tested against the second set of objects, utilizing the single instruction multiple data processing architecture.

US Patent:

8072460, Dec 6, 2011

Filed:

Oct 17, 2007

Appl. No.:

11/874093

Inventors:

Christian Lauterbach - Carrboro NC, US
David Patrick Luebke - Charlottesville VA, US
Michael J. Garland - Lake Elmo MN, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 15/80
G06F 15/00
G06T 1/00

US Classification:

345505, 345501

Abstract:

A system, method, and computer program product are provided for generating a ray tracing data structure utilizing a parallel processor architecture. In operation, a global set of data is received. Additionally, a data structure is generated utilizing a parallel processor architecture including a plurality of processors. Such data structure is adapted for use in performing ray tracing utilizing the parallel processor architecture, and is generated by allocating the global set of data among the processors such that results of processing of at least one of the processors is processed by another one of the processors.

US Patent:

8200947, Jun 12, 2012

Filed:

Mar 24, 2008

Appl. No.:

12/054322

Inventors:

John R. Nickolls - Los Altos CA, US
Lars Nyland - Carrboro NC, US
Peter C. Mills - San Jose CA, US
Jeremy Sugerman - Palo Alto CA, US
Timothy Foley - Pleasant Hill CA, US
Brian Fahs - Los Altos CA, US
Michael Garland - Lake Elmo MN, US
David P. Luebke - Charlottesville VA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 9/00

US Classification:

712220, 714797

Abstract:

One embodiment of the present invention sets forth a technique for efficiently performing voting operations within a multi-threaded parallel-processing system. A group of related parallel program threads executes within a processor core together in parallel. A new instruction, called a “vote” instruction, is introduced that enables a parallel program thread to post an individual vote within the context of the group of related threads and to receive the result of the vote. In this fashion, the vote instruction advantageously reduces overhead associated with inter-thread communication, thereby improving overall system performance.

US Patent:

8214625, Jul 3, 2012

Filed:

Nov 26, 2008

Appl. No.:

12/324645

Inventors:

John R. Nickolls - Los Altos CA, US
Lars Nyland - Carrboro NC, US
Peter C. Mills - San Jose CA, US
Jeremy Sugerman - Palo Alto CA, US
Timothy Foley - Pleasant Hill CA, US
Brian Fahs - Los Altos CA, US
Michael Garland - Lake Elmo MN, US
David P. Luebke - Charlottesville VA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 9/00

US Classification:

712220, 714797

Abstract:

One embodiment of the present invention sets forth a technique for efficiently performing voting operations within a multi-threaded parallel-processing system. A group of related parallel program threads executes within a processor core together in parallel. A new instruction, called a “vote” instruction, is introduced that enables a parallel program thread to post an individual vote within the context of the group of related threads and to receive the result of the vote. In this fashion, the vote instruction advantageously reduces overhead associated with inter-thread communication, thereby improving overall system performance.

US Patent:

8243083, Aug 14, 2012

Filed:

Dec 11, 2008

Appl. No.:

12/333255

Inventors:

Michael J. Garland - Lake Elmo MN, US
Shubhabrata Sengupta - Davis CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 15/80

US Classification:

345505, 345419, 345501, 345506, 712 2, 712 10

Abstract:

A system, method, and computer program product are provided for converting a scan algorithm to a segmented scan algorithm in an operator independent manner. In operation, a scan algorithm and a limit index data structure are identified. Utilizing the limit index data structure, the scan algorithm is converted to a segmented scan algorithm in an operator-independent manner. Additionally, the segmented scan algorithm is performed to produce an output.

US Patent:

8264484, Sep 11, 2012

Filed:

Oct 29, 2007

Appl. No.:

11/927159

Inventors:

Christian Lauterbach - Carrboro NC, US
David Patrick Luebke - San Jose CA, US
Michael J. Garland - Lake Elmo MN, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06T 15/00

US Classification:

345419

Abstract:

A system, method, and computer program product are provided for organizing a plurality of rays. In operation, a plurality of rays is identified. Additionally, the rays are organized, utilizing a bounding volume.

US Patent:

8284188, Oct 9, 2012

Filed:

Oct 29, 2007

Appl. No.:

11/927099

Inventors:

Christian Lauterbach - Carrboro NC, US
David Patrick Luebke - San Jose CA, US
Michael J. Garland - Lake Elmo MN, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06T 15/00

US Classification:

345419

Abstract:

A ray tracing system, method, and computer program product are provided for simultaneously traversing a hierarchy of rays and a hierarchy of objects. In operation, a hierarchy of rays and a hierarchy of objects are simultaneously traversed. Additionally, ray tracing is performed, based on the traversal.

US Patent:

8321492, Nov 27, 2012

Filed:

Dec 11, 2008

Appl. No.:

12/333244

Inventors:

Shubhabrata Sengupta - Davis CA, US
Michael J. Garland - Lake Elmo MN, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 15/80

US Classification:

708620, 345505, 345501

Abstract:

A system, method, and computer program product are provided for converting a reduction algorithm to a segmented reduction algorithm. In operation, a reduction algorithm is identified. Additionally, the reduction algorithm is converted to a segmented reduction algorithm. Furthermore, the segmented reduction algorithm is performed to produce an output.