Michael I Current

Author:

Michael I. Current

ISBN #:

0892525657

US Patent:

7019513, Mar 28, 2006

Filed:

Jan 19, 2005

Appl. No.:

11/040791

Inventors:

Vladimir Faifer - San Jose CA, US
Phuc Van - San Jose CA, US
Michael Current - San Jose CA, US
Timothy Wong - San Jose CA, US

International Classification:

G01R 31/28

US Classification:

3241581

Abstract:

A contactless sheet resistance measurement apparatus and method for measuring the sheet resistance of a surface p-n junction and its leakage current is disclosed. The apparatus comprises an alternating light source optically coupled with a transparent and conducting electrode brought close to the junction, a second electrode placed outside of the illumination area, and a third grounded electrode surrounding the first and second electrodes. For measurements of junction capacitance, a calibration wafer with known sheet resistance is used to provide reference photovoltage signals. Using the measurement of the junction photovoltage (JPV) signals from the illuminated area and outside this area for calibration and test wafers at different light modulation frequencies, p-n junction sheet resistance and conductance (leakage current density) are determined.

US Patent:

7414409, Aug 19, 2008

Filed:

Aug 19, 2005

Appl. No.:

11/207918

Inventors:

Vladimir Faifer - San Jose CA, US
Michael Current - San Jose CA, US
Timothy Wong - San Jose CA, US

International Classification:

G01R 31/08
G01R 31/26

US Classification:

324522, 324765

Abstract:

A non-contact apparatus and method for measuring of the leakage current and capacitance of p-n junctions in test structures within scribe lanes of IC product wafers is disclosed. The apparatus has a light source optically coupled with a fiber to a transparent electrode at the end of the fiber, which is brought close to the p-n junction under test. The ac signal generated from the test p-n junction is captured by this transparent and conducting coating electrode. The leakage current of a test p-n junction is determined using the frequency dependence of junction photo-voltage signal and reference signals from a p-n junction with low leakage current and known capacitance.

US Patent:

7642772, Jan 5, 2010

Filed:

Nov 5, 2007

Appl. No.:

11/982624

Inventors:

Vladimir Faifer - Mountain View CA, US
Michael Current - San Jose CA, US
Timothy Wong - Cupertino CA, US

Assignee:

Ahbee 1, L.P. - San Jose CA

International Classification:

G01R 31/28

US Classification:

3241581

Abstract:

A non-contact apparatus and method for measuring of the leakage current and capacitance of p-n junctions in test structures within scribe lanes of IC product wafers is disclosed. The apparatus comprises of a light source optically coupled with a fiber to a transparent electrode at the end of the fiber, which is brought close to the p-n junction under test. The ac signal generated from the test p-n junction is captured by this transparent and conducting coating electrode. The leakage current of a test p-n junction is determined using the frequency dependence of junction photo-voltage signal and reference signals from a p-n junction with low leakage current and known capacitance.

US Patent:

D645768, Sep 27, 2011

Filed:

Apr 7, 2010

Appl. No.:

29/349483

Inventors:

Yuen Lim - San Jose CA, US
Michael Current - San Jose CA, US

Assignee:

Abhee 1, L.P. - Los Altos CA

International Classification:

1004

US Classification:

D10 78

US Patent:

8187377, May 29, 2012

Filed:

Oct 4, 2002

Appl. No.:

10/264393

Inventors:

Igor J. Malik - Palo Alto CA, US
Sien G. Kang - Dublin CA, US
Martin Fuerfanger - San Jose CA, US
Harry Kirk - Campbell CA, US
Ariel Flat - Palo Alto CA, US
Michael Ira Current - San Jose CA, US
Philip James Ong - Milpitas CA, US

Assignee:

Silicon Genesis Corporation - San Jose CA

International Classification:

C30B 33/00

US Classification:

117 3, 117 97, 117928, 117939, 438689, 438706

Abstract:

The present invention provides for treating a surface of a semiconductor material. The method comprises exposing the surface of the semiconductor material to a halogen etchant in a hydrogen environment at an elevated temperature. The method controls the surface roughness of the semiconductor material. The method also has the unexpected benefit of reducing dislocations in the semiconductor material.

US Patent:

50476483, Sep 10, 1991

Filed:

Nov 26, 1990

Appl. No.:

7/618019

Inventors:

Boris Fishkin - San Jose CA
Michael Current - Mountain View CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01J 37244

US Classification:

2504922

Abstract:

A method for detecting particles in an ion implantation characterized by the steps of placing a particle sensor within the vacuum chamber of the ion implantation machine, exposing the substrate to an ion beam, thereby dislodging a stream of free particles, and detecting a portion of the free particle sensor. The particle sensor is preferably shielded from radiation to prevent false readings, and is positioned substantially along the plane of rotation of a substrate support wheel. By positioning the particle counter both along the plane of rotation and tangential to the rotation of the wheel at the point of ion impact, the particle counter intercepts the particle stream at the point of maximum particle flux. The apparatus includes a laser beam, a photodetector responsive to a portion of the laser beam scattered off of particles in the particle stream and a lead shield to shield the photodetector from x-rays generated within the vacuum chamber of the ion implantation machine.

US Patent:

20210242184, Aug 5, 2021

Filed:

Feb 12, 2021

Appl. No.:

17/175357

Inventors:

- Fremont CA, US
Michael I. CURRENT - San Jose CA, US

International Classification:

H01L 25/10
H01L 21/822
H01L 25/00
H01L 21/762
H01L 23/00

Abstract:

A method of forming a semiconductor device includes providing a semiconductor substrate with a circuit layer, forming a range compensating layer over the semiconductor substrate, the range compensating layer having a plurality of different thicknesses, each of the plurality of different thicknesses being inversely proportional to a stopping power of structures disposed under the respective thickness of the range compensating layer, implanting ions into the semiconductor substrate, the ions traveling through the range compensating layer and the circuit layer to define a cleave plane in the semiconductor substrate, removing the range compensating layer, and cleaving the semiconductor substrate at the cleave plane. The range compensating layer can be used to compensate for variations in ion penetration depth.

US Patent:

20210020452, Jan 21, 2021

Filed:

Jul 15, 2020

Appl. No.:

16/947034

Inventors:

Thomas E Seidel - Palm Coast FL, US
Michael I Current - San Jose CA, US

International Classification:

H01L 21/311
H01L 21/3065
H01L 21/3213

Abstract:

Processes for the localized etching of films on the sidewalls of non-planar 3D features such as a trench or a FinFET array. The etch process has a first step of an angle-directed ion implant beam, with the beam being self-aligned onto a localized region on a sidewall feature, that functionalizes the region for a second step that etches the ion implanted region.