Mark Ronald Eliscu

US Patent:

46445293, Feb 17, 1987

Filed:

Aug 2, 1985

Appl. No.:

6/762592

Inventors:

Stanford R. Amstutz - Andover MA
Mark Eliscu - Needham MA
Pamidimukkala M. V. Rao - Boston MA

Assignee:

GTE Laboratories Incorporated - Waltham MA

International Classification:

H04J 600

US Classification:

370 60

Abstract:

This invention provides a high-speed switching processor which may be employed as a component of a link switch or a hub switch in a burst-switching communications system. When so employed, transmission speeds for integrated voice and data services over communications links between switches may be equivalent to the T1 rate or higher. A burst is a plurality of bytes which represents, for example, a block of data or a spurt of voice energy sensed by silence/voice detectors located at voice ports. In a preferred embodiment, the architecture of the switching processor includes a data/address bus, control including a stored program in a 64-bit wide PROM, a finite-state machine having character and channel states for generating a jump address in the stored program based on the status of an incoming burst, interfaces with other components of the switch such as the queue sequencer, a companion processor, and a dual-port RAM for generating a buffer address as a function of channel number for the dynamic buffer in character memory in which the incoming burst is being stored. In this architecture, most components of the switching processor operate substantially in parallel with and independently of the control which is a contributing factor to the overall speed advantage realized by the switching processor. With software or firmware variations, the switching processor may be employed as several different components of a link or hub switch.

US Patent:

46987991, Oct 6, 1987

Filed:

Aug 2, 1985

Appl. No.:

6/762641

Inventors:

Stanford R. Amstutz - Andover MA
Mark Eliscu - Needham MA
E. Fletcher Haselton - Waltham MA

Assignee:

GTE Laboratories Incorporated - Waltham MA

International Classification:

H04Q 1104

US Classification:

370 58

Abstract:

A high-speed link switch for a distributed-control burst-switching communications system. The switch provides fully integrated voice and data services and processing capacity sufficient to support T1 or higher transmission rates. A communications systems may include a plurality of switches interconnected by time-division multiplexed links. In a preferred embodiment, a link switch comprises a central memory coupled with a link-input processor, a link-output processor, a port-input processor, a port-output processor, and a memory manager. The link switch includes switching intelligence for routing a burst through the switch toward its destination port in the system. A burst is a plurality of bytes which may represent, for example, a block of data or a spurt of voice energy as sensed by silence/voice detectors located at voice ports. Within an outgoing communications link, a burst is transmitted by a switch one byte at a time in an assigned channel of sequential frames of the time-division multiplexed link. The routine intelligence employs dynamic allocation of bursts to channels within communications links such that any channel of a communications link is allocated only when a burst is being transmitted therein and such channel is otherwise available for transmission of another burst.

US Patent:

47109165, Dec 1, 1987

Filed:

Aug 2, 1985

Appl. No.:

6/762589

Inventors:

Stanford R. Amstutz - Andover MA
Mark Eliscu - Needham MA
Joseph M. Lenart - Arlington MA
E. Fletcher Haselton - Waltham MA

Assignee:

GTE Laboratories Incorporated - Waltham MA

International Classification:

H04Q 1104

US Classification:

370 58

Abstract:

A burst-switching communications system with integrated voice and data services and with processing capacity sufficient to support T1 or higher link transmission rates, such system including a hub switch located at a point of high-traffic concentration in the network and a plurality of link switches. The switches are interconnected by time-division multiplexed communications links. A burst is a variable-length sequence of bytes which represents, for example, a block of data or a spurt of voice energy as sensed by silence/voice detectors located at voice ports. Within a communications link, a burst is transmitted one byte at a time in an assigned channel of sequential frames of the time-division multiplexed link. The hub switch includes a number of switching units connected in a closed hub ring with one or more time-division multiplexed communication link to another communication link as determined by address information in the burst being received. The bytes of a burst are transferred along the hub ring from the switching unit of the incoming communication link to the switching unit of the outgoing communication link in sequential frames of time-division multiplexed hub channels.

US Patent:

46462945, Feb 24, 1987

Filed:

Aug 2, 1985

Appl. No.:

6/762642

Inventors:

Mark Eliscu - Needham MA
Stanford R. Amstutz - Andover MA
Pamidimukkala M. V. Rao - Boston MA

Assignee:

GTE Laboratories Incorporated - Waltham MA

International Classification:

H04J 600

US Classification:

370 94

Abstract:

This invention provides a high-speed queue sequencer which may be employed as a component of a link switch or hub switch in a burst-switching communications system. When so employed, transmission speeds for integrated voice and data services over communications links between switches may be equivalent to the T1 rate or higher. A burst is a plurality of bytes which represents, for example, a block of data or a spurt of voice energy sensed by silence/voice detectors located at voice ports. In a preferred embodiment, the architecture of the queue sequencer includes a data/address bus, control including a stored program in a 64-bit wide PROM, a random-access memory for queue memory which stores administrative information pertaining to bursts passing through the switch, enque means for adding a burst to the list of bursts awaiting assignment to an output channel, and deque means for assigning the highest-priority burst on this list to an output channel and removing the burst from the list, first-in first-out memory for storing requests from switching processors and providing these requests to the control of the queue sequencer within priority class in the same time order as received, and input and output interfaces for coupling with the switching processors. A switching processor is a companion high-speed processor employed as one or more components in a link switch and hub switch. Most components of the queue sequencer operate substantially in parallel with and independently of the control, which is a contributing factor to the speed advantage realized by the queue sequencer.