Manu Mishra

US Patent:

7642853, Jan 5, 2010

Filed:

Aug 23, 2007

Appl. No.:

11/844314

Inventors:

Hayg-Taniel Dabag - Bochum, DE
Dongwon Seo - San Diego CA, US
Manu Mishra - San Diego CA, US

Assignee:

QUALCOMM, Incorporated - San Diego CA

International Classification:

H03F 3/26

US Classification:

330267, 330261

Abstract:

An output stage includes two transistors (switching transistor and biasing transistor) coupled in series in a pullup current path between a VDDA node and an output node, and also includes two transistors (switching transistor and biasing transistor) coupled in series in a pulldown current path between the output node and a ground node. Providing the biasing transistors reduces the maximum voltage dropped across the transistors, thereby allowing the transistors to have lower breakdown voltages than VDDA. An adaptive biasing circuit adjusts the gate voltage on a biasing transistor based on the output node voltage. If the output voltage is in a midrange, then the gate voltage is set farther away from a rail voltage in order to reduce voltage stress. If the output voltage is in a range closer to the rail voltage, then the gate voltage is set closer to the rail voltage, thereby facilitating rail-to-rail output voltage swings.

US Patent:

20080309537, Dec 18, 2008

Filed:

Jun 14, 2007

Appl. No.:

11/762884

Inventors:

Dongwon Seo - San Diego CA, US
Bo Sun - Carlsbad CA, US
Gurkanwal S. Sahota - San Diego CA, US
Manu Mishra - San Diego CA, US

International Classification:

H03M 1/66

US Classification:

341144

Abstract:

A digital-to-analog converter, RF transmit channel and method, for converting a digital signal of N bits having a set M of most significant bits and a set L of least significant bits to an analog signal, are disclosed. The digital signal defines a set of coded values which are converted to analog values and modulated on to a RF signal. The digital-to-analog converter includes a plurality of switches and an output stage, for providing at least a first differential output signal and a second differential output signal. The output stage modifies currents received from the plurality of switches, such that the value of the average output current of the first and second differential outputs signals is steered to a relatively low current value at the mid-point of the coded values.

US Patent:

20150381119, Dec 31, 2015

Filed:

Jun 30, 2014

Appl. No.:

14/320118

Inventors:

- San Diego CA, US
Ankit Srivastava - San Diego CA, US
Matthew David Sienko - San Diego CA, US
Manu Mishra - San Diego CA, US
Sheng Zhang - San Jose CA, US

International Classification:

H03F 1/32
H03F 3/217
H03F 3/185

Abstract:

A switching amplifier includes a compensation circuit to compensate for DC offset in the amplifier, to enhance operation of the switching amplifier. The compensation circuit may comprise a SAR ADC, where the DAC element can be used to provide a compensation voltage. The switching amplifier may further include a PWM modulator configured to avoid cross-talk to further enhance operation of the switching amplifier.

US Patent:

20150263676, Sep 17, 2015

Filed:

Mar 14, 2014

Appl. No.:

14/210905

Inventors:

- San Diego CA, US
Matthew David Sienko - San Diego CA, US
Ankit Srivastava - San Diego CA, US
Manu Mishra - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03F 1/02
H03F 3/45
H03F 3/185

Abstract:

An apparatus includes voltage-to-current conversion circuitry comprising a first voltage-to-current converter and a second voltage-to-current converter. The apparatus also includes a capacitor coupled to the first voltage-to-current converter and to the second voltage-to-current converter.