Lloyd G Burrell

US Patent:

6908841, Jun 21, 2005

Filed:

Sep 20, 2002

Appl. No.:

10/251453

Inventors:

Lloyd G. Burrell - Poughkeepsie NY, US
Douglas Kemerer - Essex Junction VT, US
Hans-Joachim Barth - Munich, DE
Emmanuel F. Crabbe - Chappaqua NY, US
David Anderson - Gulf Shores AL, US
Joseph Chan - Fishkill NY, US

Assignee:

Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY

International Classification:

H01L021/44

US Classification:

438612

Abstract:

A semiconductor device () having support structures () beneath wirebond regions () of contact pads () and a method of forming same. Low modulus dielectric layers () are disposed over a workpiece (). Support structures () are formed in the low modulus dielectric layers (), and support vias () are formed between the support structures (). A high modulus dielectric film () is disposed between each low modulus dielectric layer (), and a high modulus dielectric layer () is disposed over the top low modulus dielectric layer (). Contact pads () are formed in the high modulus dielectric layer (). Each support via () within the low modulus dielectric layer () resides directly above a support via () in the underlying low modulus dielectric layer (), to form a plurality of via support stacks within the low modulus dielectric layers ().

US Patent:

6960831, Nov 1, 2005

Filed:

Sep 25, 2003

Appl. No.:

10/605369

Inventors:

Lloyd G. Burrell - Poughkeepsie NY, US
Kwong H. Wong - Wappingers Falls NY, US
Adreanne A. Kelly - Poughkeepsie NY, US
Samuel R. McKnight - New Paltz NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L023/48

US Classification:

257751, 257763, 257764, 257781

Abstract:

A semiconductor device, and a method of fabricating the device, having a copper wiring level and an aluminum bond pad above the copper wiring level. In addition to a barrier layer which is normally present to protect the copper wiring level, there is a composite layer between the aluminum bond pad and the barrier layer to make the aluminum bond pad more robust so as to withstand the forces of bonding and probing. The composite layer is a sandwich of a refractory metal and a refractory metal nitride.

US Patent:

7037824, May 2, 2006

Filed:

May 13, 2004

Appl. No.:

10/844533

Inventors:

Lloyd G. Burrell - Poughkeepsie NY, US
Jeffrey P. Gambino - Westford VT, US
Hyun Koo Lee - LaGrangeville NY, US
Mark D. Levy - Essex Junction VT, US
Baozhen Li - South Burlington VT, US
Stephen E. Luce - Underhill VT, US
Thomas L. McDevitt - Underhill VT, US
Anthony K. Stamper - Williston VT, US
Kwong Hon Wong - Wappingers Falls NY, US
Sally J. Yankee - Underhill VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/4763

US Classification:

438627, 438629, 438643, 438648, 438653, 438687

Abstract:

Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.

US Patent:

7087997, Aug 8, 2006

Filed:

Mar 12, 2001

Appl. No.:

09/805027

Inventors:

Lloyd G. Burrell - Poughkeepsie NY, US
Jeffrey P. Gambino - Westford VT, US
Hyun Koo Lee - LaGrangeville NY, US
Mark D. Levy - Essex Junction VT, US
Baozhen Li - South Burlington VT, US
Stephen E. Luce - Underhill VT, US
Thomas L. McDevitt - Underhill VT, US
Anthony K. Stamper - Williston VT, US
Kwong Hon Wong - Wappingers Falls NY, US
Sally J. Yankee - Underhill VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257750, 257761, 257762, 257763, 257764, 257770

Abstract:

Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.

US Patent:

7250311, Jul 31, 2007

Filed:

Feb 23, 2005

Appl. No.:

10/906507

Inventors:

Toyohiro Aoki - Yasu, JP
Lloyd G. Burrell - Poughkeepsie NY, US
Wolfgang Sauter - Richmond VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/66
H01L 23/48

US Classification:

438 14, 438614, 257781, 257784

Abstract:

A sensor for measuring cracks in a semiconductor device, such as a wafer and, more particularly, to a BEOL wirebond crack sensor for low-k dies or wafers, and a method of providing the wirebond crack sensor for low-k wafers or the like structures.

US Patent:

7294565, Nov 13, 2007

Filed:

Oct 1, 2003

Appl. No.:

10/676172

Inventors:

Lloyd G. Burrell - Poughkeepsie NY, US
Charles R. Davis - Fishkill NY, US
Ronald D. Goldblatt - Yorktown Heights NY, US
William F. Landers - Wappingers Falls NY, US
Sanjay C. Mehta - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/28
H01L 23/48

US Classification:

438582, 438612, 438614, 438617, 438648, 257763, 257765, 257770

Abstract:

A method for sealing an exposed surface of a wire bond pad with a material that is capable of preventing a possible chemical attack during electroless deposition of Ni/Au pad metallurgy is provided. Specifically, the present invention provides a method whereby a TiN/Ti or TiN/Al cap is used as a protective coating covering exposed surfaces of a wire bond pad. The TiN/Ti or TiN/Al cap is not affected by alkaline chemistries used in forming the Ni/Au metallization, yet it provides a sufficient electrical pathway connecting the bond pads to the Ni/Au pad metallization.

US Patent:

7405108, Jul 29, 2008

Filed:

Nov 20, 2004

Appl. No.:

10/994494

Inventors:

Lloyd G. Burrell - Poughkeepsie NY, US
Howard Hao Chen - Yorktown Heights NY, US
Louis L. Hsu - Fishkill NY, US
Wolfgang Sauter - Richmond VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00

US Classification:

438125, 438464, 257E21122

Abstract:

Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.

US Patent:

7867820, Jan 11, 2011

Filed:

May 15, 2008

Appl. No.:

12/121468

Inventors:

Lloyd G. Burrell - Poughkeepsie NY, US
Howard Hao Chen - Yorktown Heights NY, US
Louis L. Hsu - Fishkill NY, US
Wolfgang Sauter - Richmond VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00

US Classification:

438107, 438113, 438114, 257E21122

Abstract:

Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.