Layne G Bunker

Address:

10975 W Hazelwood Dr, Boise, ID 83709

Phone:

2088906241

VIN:

5TFBV54147X024622

Make:

TOYOTA

Model:

TUNDRA

Year:

2007

US Patent:

6400595, Jun 4, 2002

Filed:

Jul 20, 2000

Appl. No.:

09/620606

Inventors:

Brent Keeth - Boise ID
Layne G. Bunker - Boise ID
Scott J. Derner - Meridian ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 502

US Classification:

365 51, 365226

Abstract:

A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. A powerup sequence circuit is provided to control the powerup of the chip.

US Patent:

6452825, Sep 17, 2002

Filed:

Jul 13, 2000

Appl. No.:

09/615496

Inventors:

Brent Keeth - Boise ID
Layne G. Bunker - Boise ID
Ronald L. Taylor - Meridian ID
John S. Mullin - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 502

US Classification:

365 51, 36523002

Abstract:

A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. In certain of the gap cells, multiplexors are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data writes muxes for providing data to the array I/O blocks. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

US Patent:

6477073, Nov 5, 2002

Filed:

Mar 9, 2001

Appl. No.:

09/801727

Inventors:

Brent Keeth - Boise ID
Layne G. Bunker - Boise ID
Larry D. Kinsman - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 502

US Classification:

365 51, 365 59

Abstract:

A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, which are organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays; row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in peripheral circuits.

US Patent:

6556065, Apr 29, 2003

Filed:

Jul 21, 2000

Appl. No.:

09/621560

Inventors:

Brent Keeth - Boise ID
Layne G. Bunker - Boise ID
Scott J. Derner - Meridian ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G05F 1100

US Classification:

327536, 363 60

Abstract:

A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits.

US Patent:

RE38109, May 6, 2003

Filed:

Dec 20, 2001

Appl. No.:

10/029572

Inventors:

Todd A. Merritt - Boise ID
Layne Bunker - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

36518902, 36518904, 3652385

Abstract:

A block write circuit in a memory device having a wide internal data path performs block write and data masking functions. The memory device includes a plurality of data terminals adapted to receive respective data signals, and a plurality of array groups each including a plurality of arrays and each array includes a plurality of memory cells. A plurality of input/output line groups each include a plurality of input/output lines coupled to the arrays of an associated array group. The block write circuit comprises a plurality of write driver groups, each write driver group including a plurality of write driver circuits having outputs coupled to respective data lines in an associated data line group. Each write driver circuit includes an input and develops a data signal on its output responsive to a data signal applied on its input. A multiplexer circuit includes a plurality of inputs coupled to respective data terminals, and a plurality of output subgroups.

US Patent:

6580631, Jun 17, 2003

Filed:

Aug 8, 2001

Appl. No.:

09/924648

Inventors:

Brent Keeth - Boise ID
Layne G. Bunker - Boise ID
Scott J. Derner - Meridian ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H03L 700

US Classification:

365143, 327198

Abstract:

A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits.

US Patent:

6594168, Jul 15, 2003

Filed:

Jun 13, 2001

Appl. No.:

09/880747

Inventors:

Brent Keeth - Boise ID
Layne G. Bunker - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 502

US Classification:

365 51, 365226

Abstract:

A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits.

US Patent:

6597206, Jul 22, 2003

Filed:

Aug 1, 2001

Appl. No.:

09/920166

Inventors:

Brent Keeth - Boise ID
Layne G. Bunker - Boise ID
Scott J. Derner - Meridian ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G01R 1900

US Classification:

327 52, 327 55

Abstract:

A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mix, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltage needed in the array and in the peripheral circuits.